ISL98003CNZ-165 Intersil, ISL98003CNZ-165 Datasheet
ISL98003CNZ-165
Specifications of ISL98003CNZ-165
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ISL98003CNZ-165 Summary of contents
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... Triple Analog-to-Digital Converters with Oversampling Video Modes • Fast Automatic Selection of Best Sampling Phase • 165MSPS Maximum Conversion Rate (ISL98003CNZ-165) • Robust, Glitchless Macrovision™-Compliant Sync Separator • Analog VCR “Trick Mode” Support • ABLC for Perfect Black Level Performance • ...
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... ISL98003INZ-110 ISL98003CNZ-110 ISL98003CNZ-150 ISL98003CNZ-165 ISL98003CNZ-EVALZ NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...
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... Operating Conditions Temperature Range ISL98003INZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C ISL98003CNZ 0°C to +70°C Supply Voltage Range . . . . . . . . . . . . . . . . . 3.3V ±10%, 1.8V ±10% CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty ...
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Electrical Specifications Specifications apply for V pixel rate = 110MHz for ISL98003-110, 150MHz for ISL98003-150 and 165MHz for ISL98003-165, f XTAL SYMBOL PARAMETER Offset Adjustment Range (ABLC Enabled or Disabled) ANALOG VIDEO INPUT CHARACTERISTICS (R Input Range Input Bias Current ...
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Electrical Specifications Specifications apply for V pixel rate = 110MHz for ISL98003-110, 150MHz for ISL98003-150 and 165MHz for ISL98003-165, f XTAL SYMBOL PARAMETER V Analog Supply Voltage, 1.8V A1.8 V Digital Supply Voltage, 3.3V D3.3 V Digital Supply Voltage, 1.8V ...
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Timing Diagrams Data Output Setup and Hold Timing DATACLK DATACLK PIXEL DATA RGB Output Data Timing and Latency HSYNC IN ANALOG VIDEO IN DATACLK R/G/B[7:0] HS OUT YUV Output Data Timing and Latency HSYNC IN ANALOG ...
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Pinout D3.3 DATACLK DATACLK HS OUT HSYNC OUT VSYNC OUT INT DE FIELD TEST OUT Pin Descriptions SYMBOL Analog inputs. Red channels. AC-couple through ...
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Pin Descriptions (Continued) SYMBOL CLAMP Digital 3.3V input.When this input is high and external CLAMP is selected, connects the selected channels inputs to the IN clamp DAC. CLOCKINV Digital 3.3V input. When high, changes the pixel sampling phase by 180°. ...
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Sync Flow 3 165 MHZ CH0 3 TRIPLE 8- BIT 3 CH1 AFE SOG SLICER A SOG0 SOG1 SOG SLICER B HSYNC SLICER A HSYNC0 HSYNC1 HSYNC SLICER B VSYNC SLICER A VSYNC0 VSYNC1 VSYNC SLICER B CH0 AND CH1 ...
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Register Listing REGISTER ADDRESS (DEFAULT VALUE) STATUS AND INTERRUPT REGISTERS 0x01 Selected Input Channel Characteristics, (read only) 0x02 CH0 and CH1 Activity Status, (read only) 0x03 Not Used (read only) 10 ISL98003 BITS FUNCTION NAME 1:0 SYNC Type 00: Automatic ...
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Register Listing (Continued) REGISTER ADDRESS (DEFAULT VALUE) 0x04 Interrupt Status, Write each bit to clear it, 0xFF to clear all. 0x05 Interrupt Mask Register, (0xFF) 11 ISL98003 BITS FUNCTION NAME 0 CH0 Sync Changed 0: No change ...
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Register Listing (Continued) REGISTER ADDRESS (DEFAULT VALUE) CONFIGURATION REGISTERS 0x10 Input Configuration, (0x00) 0x11 Sync Source Selection, (0x00) 0x12 Red Gain MSB, (0x55) 0x13 Red Gain LSB, (0x00) 0x14 Green Gain MSB, (0x55) 0x15 Green Gain LSB, (0x00) 0x16 Blue ...
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Register Listing (Continued) REGISTER ADDRESS (DEFAULT VALUE) 0x1A Green Offset MSB, (0x80) 0x1B Green Offset LSB, (0x00) 0x1C Blue Offset MSB, (0x80) 0x1D Blue Offset LSB, (0x00) 0x1E PLL HTOTAL MSB, (0x06) 0x1F PLL HTOTAL LSB, (0x98) 0x20 PLL Phase, ...
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Register Listing (Continued) REGISTER ADDRESS (DEFAULT VALUE) 0x27 ABLC Configuration, (0x40) 0x28 Output Format 1, (0x00) 14 ISL98003 BITS FUNCTION NAME 0 ABLC Disable 0: ABLC on (default) - use 8-bit digital offset control. 0x000 = -0x200 LSB offset, 0x3FF ...
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Register Listing (Continued) REGISTER ADDRESS (DEFAULT VALUE) 0x29 Output Format 2, (0x00) 0x2A HSOUT Width, (0x10) 0x2B Output Signal Disable, (0xFF) Note: All digital outputs are tri-stated by default to ease multiplexing with other AFEs 0x2C Power Control, (0x00) 15 ...
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Register Listing (Continued) REGISTER ADDRESS (DEFAULT VALUE) 0x2D XTAL CLOCK FREQ, (0x19) 0x2E AFE Bandwidth, (0x0E) 0x2F HSYNC Slicer Thresholds, (0x44) All values referred to voltage at HSYNC input pin, 300mV hysteresis 0x30 SOG Slicer Thresholds, (0x66) 16 ISL98003 BITS ...
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Register Listing (Continued) REGISTER ADDRESS (DEFAULT VALUE) 0x31 HSYNC/SOG Config, (0x04) 0x32 Sync Polling Control, (0x00) MEASUREMENT REGISTERS 0x40 HSYNC Period MSB, (read only) 0x41 HSYNC Period LSB, (read only) 0x42 HSYNC Width MSB, (read only) 0x43 HSYNC Width LSB, ...
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Register Listing (Continued) REGISTER ADDRESS (DEFAULT VALUE) 0x44 VSYNC Period MSB, (read only) 0x45 VSYNC Period LSB, (read only) 0x46 VSYNC Width, (read only) 0x47 DE Start MSB, (0x00) 0x48 DE Start LSB, (0xF6) 0x49 DE Width MSB, (0x05) 0x4A ...
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Register Listing (Continued) REGISTER ADDRESS (DEFAULT VALUE) 0x52 Phase ADJ MASK V, (0x01) 0x53 Horizontal pixel mask 1, (0x01) 0x54 Horizontal pixel mask 2, (0x01) 0x55 Phase Adjust Command Options, (0x20) 19 ISL98003 BITS FUNCTION NAME 2:0 PADJ Exclude v2 ...
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Register Listing (Continued) REGISTER ADDRESS (DEFAULT VALUE) 0x56 Transition threshold, (0x0A) 0x57 Phase Adjust Data 3, (read only) 0x58 Phase Adjust Data 2, (read only) 0x59 Phase Adjust Data 1, (read only) 0x5A Phase Adjust Data 0, (read only) 0x60 ...
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Technical Highlights The ISL98003 provides all the features of traditional triple channel video AFEs, but adds several next-generation enhancements, bringing performance and ease of use to new levels. DPLL All video AFEs must phase lock to an HSYNC signal, supplied ...
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The offset controls shift the entire RGB input range, changing the input image brightness. Three separate registers provide independent control of the R, G, and B channels. Their nominal setting is 0x8000, which forces the ADC to output code 0x00 ...
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DC Restoration V CLAMP DC Restore Clamp DAC GENERATION R(GB VGA0 V + R(GB GND PGA R(GB VGA1 R(GB) 1 GND SOG For component YPbPr signals, the sync signal is embedded ...
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... Intersil’s DPLL has the capability to correct large phase changes almost instantly by maximizing the phase error gain while keeping the frequency gain relatively low. This is done by changing the contents of register 0x74 to 0x4C. This increases the phase error gain to 100%. Because a phase ...
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The default Offset DAC range is ±127 ADC LSBs. Setting 0x27[ reduces the swing of the Offset DAC by 50%, making 1 Offset DAC LSB the weight of 1 ADC LSB. This provides the finest offset ...
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SOG activity when there actually is no SOG signal, while non-standard SOG signals and TriLevel sync signals may have amplitudes below the default SOG slicer levels and not be easily detected consequence, not all ...
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... If the databus is lightly loaded, it may be increased. Intersil’s recommendations to minimize EMI are: • Minimize the databus trace length • Minimize the databus capacitive loading. If EMI is a problem in the final design, increase the value of the digital output series resistors to reduce slew rates on the bus. This can only be done as long as the scaler’ ...
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Once the serial address has been transmitted and acknowledged, one or more bytes of information can be written to or read from the slave. Communication with the selected device in the selected direction (read or write) is ended by a ...
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START COMMAND ISL98003 SERIAL BUS ADDRESS (REPEAT IF DESIRED) STOP COMMAND S T REGISTER SERIAL BUS A SIGNALS ADDRESS R ADDRESS FROM THE T HOST ...
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START COMMAND ISL98003 SERIAL BUS ADDRESS START COMMAND ISL98003 SERIAL BUS (REPEAT IF DESIRED) STOP COMMAND S T SERIAL BUS ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...