E-STLC7550TQF7 STMicroelectronics, E-STLC7550TQF7 Datasheet
E-STLC7550TQF7
Specifications of E-STLC7550TQF7
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E-STLC7550TQF7 Summary of contents
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... The STLC7550 is a single chip Analog Front-end (AFE) designed to implement modems up to 56Kbps. Order codes Part number STLC7550 TQF7 STLC7550 TQF7TR E-STLC7550TQF7 (*) ® (*) ECOPACK (see Section 6) February 2006 Low Power Low Voltage Analog Front End It has been especially designed for host processing application in which the modulation software (V ...
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... Receive A/D section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.1 2.2.2 2.3 Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5 Host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.6 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 Nominal DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 Nominal AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 Transmit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.1 3.4.2 3.5 Receive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5.1 4 Typical application ...
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... Positive Digital Power Supply (2.7V TO 5.5V) DD DGND I Digital Ground MCM I Master Clock Mode XTALOUT O Crystal Output XTALIN/MCLK I Crystal Input (MCM = 1) / External Clock (MCM = 0) HC1 I Hardware Control Input HC0 I Hardware Control Input PWRDWN I Power down Input M/S I Master/Slave Mode Control Pin Input ...
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... Supply (AV DD This pin is the positive analog power supply voltage for the DAC and the ADC section not internally connected to digital V In any case the voltage on this pin must be higher or equal to the voltage of the Digital power supply ( Digital VDD Supply (DVDD) This pin is the positive digital power supply for DAC and ADC digital internal circuitry ...
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... After a low-going pulse on RESET, the device registers will be initialized to provide an over-sampling ratio equal to 160, the serial interface will be in data mode, the DAC attenuation will be set to infinite, the ADC gain will be set to 0dB, the Differential input mode on the ADC converter will be selected, and the multiplexor will be set on the main inputs IN+ and IN- ...
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... Fs x Over (see Figure 3 Timeslot Control (TS) When the data are assigned to the first 16 bits after falling edge of FS (7546 mode) otherwise the data are bits 17 to 32. The case M with reserved for life-test (transmit gain fixed to 0dB). 1.1.3 Clock signals (2 pins) Depending on MCM value, these pins have different function. ...
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... Sigma-Delta modulator. The analog input peak-topeak differential signal range must be less than The cut-off frequency of the filter must be lower than one half the oversampling frequency. These filters should be set as close as possible to the IN+ and IN- pins. The gain of the first stage is programmable (see Non-inverting Auxiliary Analog Input (AUX IN+) This pin is the differential non-inverting auxiliary ADC input ...
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... The digital signal from the serial interface gets interpolated Sampling Frequency (FS) through the IIR filter. The signal is further interpolated (with n equal through the IIR and FIR filter. The low pass filter is followed by the DAC. The DAC is oversampled at 64, 96, 128, 160, 192 x FS. The oversampling ratio is user selectable ...
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... Clock generator The master clock, MCLK is provided by the user thanks to a crystal or external clock generator (see Figure The MCLK could be equal to 36.864MHz (MCM = 1). In that case thanks to the divider the STLC7550 is able to generate all V.34bis and 56 Kbps sampling frequencies (see Table 2). ...
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... The STLC7550 is in slave mode. SCLK is provided by the STLC7550, the processor generates the Fs and controls the phase of the sampling frequency. Fs must be the result of a division of a number of cycles of SLCK (Fs = SCLK % OVER). Configuration 3 : MCM = 0, M The STLC7550 is in master mode and the processor provides the XTAL IN = MCLK = OCLK ...
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... STLC7550 Figure 5. Configuration 2 Figure 6. Configuration 3 (7546 mode) Configuration 5 : MCM = 1, M (master codec) MCM = 0, M (slave codec) This is dual codec application. The master codec has his data in timeslot 0 and the slave codec has his data in timeslot 1 thanks to the programmation of TS. Figure 7. Configuration ...
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... When Control Mode is selected, the device will internally generate an additional Frame Synchronization Pulse (Secondary Frame Synchronization Pulse) at the midpoint of the original Frame Period. If the device is in slave mode the additional frame sync (secondary frame sync pulse) must be generated by the processor. The Original Frame Synchronization Pulse will also be referred to as the Primary Frame Synchronization Pulse ...
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... SCLK TxDI TxDO HC1, HC0 Note : In slave mode, this 1/2 Sampling Period is not mandatory. If 1/2 Sampling Period is not provided, one sample is lost. 2.6 Control register This section defines the control and device status information. The register programming occurs only during Secondary Frame Synchronization. After a reset condition, the device is always in data mode ...
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... Auxiliary Receive Input Table 6. Receive Gain D2 DIFFERENTIAL INPUT 0 0dB gain (commun mode fixed) 1 +6dB gain (commun mode non-fixed) SINGLE ENDED (one input used, other -6dB gain (see Note 1) 1 0dB gain Note: 1 Not recommended case. Performances could be reduced. Table 7. Oversampling Ratio ...
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... D10 Table 10. M Divider Clock Generator D13 D12 Table 11. Reserved Mode D15 D14 X X This two bits must be set to 0 for normal operation Reserved 128 Infinite Reserved -6dB 0dB divider = divider = divider = divider = divider = 4 divider = 5 divider = 6 divider = 7 divider = divider = 4 X Reserved X ...
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... Electrical Specifications 3 Electrical Specifications Unless otherwise noted, Electrical Characteristics are specified over the operating range. Typical values are given for V MCLK = 1.536MHz and oversampling ratio = 160. 3.1 Absolute maximum ratings Table 12. Absolute Maximum Ratings (referenced to GND) Symbol V DC Supply Voltage Digital or Analog Input Voltage ...
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... V Temperature Coefficient coeff REF REF Input Common Mode Offset Voltage V CMO [(IN+)+(IN-)]/2 -V CMO IN Differential Input Voltage : [(IN+)-(IN-)] ≤ DIF IN V Differential Input DC Offset Voltage OFF IN Output Common Mode Voltage Offset : V CMO OUT (OUT+ + OUT-)/ Differential Output Voltage : V DIF OUT OUT+ - OUT- ≤ ...
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... SCLK Rise Time 5 SCLK Fall Time 6 FS Setup 7 FS Hold 8 DIN Setup 9 DIN Hold 10 DOUT Valid 11 HC0,HC1 Set-up 12 MASTER CLOCK INTERFACE (MCLK) (MCM = 0) MCLK Master Clock Input Master Clock Duty Cycle Figure 11. Serial Interface Timing Diagram 12 SCLK DIN DOUT 11 HC0 18/24 = 0.5V ...
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... CRxTx Crosstalk (transmit channel to receive channel) Note: 1 The dynamic range can be measured in bit with : Nbit = 3.4.2 Smoothing filter transfer characteristics The cut-off frequency of the single pole switch-capacitor low-pass filter following the DAC – 3.5 Receive Characteristics 3.5.1 Performance of the Rx channel Table 16. ...
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... OUT+ OUT- IN+ IN- All capacitor, resistor and impedance values are provided for indication only. These values must be readjusted according to line transformer characteristics and also telecommunication regulations in force in individual countries. Refer to Application Note AN930 for more detailed information. Contact your local representative. ...
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... The S/(N+D) with a 1kHz, -20dBr input signal and extrapolated to full scale. Use of a small input signal reduces the harmonic distortion components of the noise to insignificance. Units S/(THD+N) is the ratio of the rms of the input signal to the rms of all other spectral components within the measurement bandwidth (0.425 x Sampling Frequency). Units in dB. ...
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... In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK trademark. ...
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... STLC7550 7 Revision history Table 17. Document revision history Date 14-Jan-2004 06-Feb-2006 Revision 8 Initial release. Removed the TQFP44 package and the respective ordering part number. 9 Inserted the new part number E-STLC7550TQF7 (ECOPACK). Rev 9 Revision history Changes 23/24 ...
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