MCP3901A0-I/SS Microchip Technology, MCP3901A0-I/SS Datasheet - Page 30

• Manufacturer Part Number: MCP3901A0-I/SS
• Description: IC AFE 24BIT 64KSPS 20-SSOP
• Manufacturer: Microchip Technology

Specifications of MCP3901A0-I/SS

• Number Of Bits: 24
• Number Of Channels: 2
• Power (watts): 10mW
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 20-SSOP
• Ic Function: Analog Front End Device IC
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: SSOP
• No. Of Pins: 20
• Supply Voltage Max: 5.5V
• Output Voltage: 0.4 V
• Output Power: 14 mW
• Input Voltage: 4.5 V to 5.5 V, 2.7 V to 5.5 V
• Switching Frequency: 4 MHz
• Mounting Style: SMD/SMT
• Number Of Outputs: 2
• No. Of Channels: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: MCP3901AO-I/SS; MCP3901AO-I/SS

MCP3901
5.8
The MCP3901 contains an internal POR circuit that
monitors analog supply voltage AV
The typical threshold for a power-up event detection is
4.2V ±5%. The POR circuit has a built-in hysteresis for
improved transient spikes immunity that has a typical
value of 200 mV. Proper decoupling capacitors (0.1 µF
ceramic and 10 µF tantalum) should be mounted as
close as possible to the AV
transient immunity.
Figure 5-4
power-up and a power-down event in the typical
conditions. All internal DC biases are not settled until at
least 50 µs after system POR. Any DR pulses during
this time, after a system Reset, should be ignored. After
POR, DR pulses are present at the pin with all the
default conditions in the Configuration registers.
Both AV
Since AV
it is highly recommended to power up DV
power-up sequence. If AV
highly recommended to keep the RESET pin low during
the whole power-up sequence.
FIGURE 5-4:
DS22192C-page 30
Device
Mode
AV
4.2V
5V
4V
0V
DD
DD
Power-on Reset
DD
and DV
is the only power supply that is monitored,
illustrates the different conditions at
Reset
50 µs
DD
t
POR
power supplies are independent.
Power-on Reset Operation.
Operation
DD
DD
Proper
is powered up first, it is
pin, providing additional
DD
during operation.
Reset
DD
first as a
Time
5.9
When the RESET pin is low, both ADCs will be in Reset
and output code, 0x0000h. The RESET pin performs a
Hard Reset (DC biases still on, part ready to convert)
and clears all charges contained in the Delta-Sigma
modulators. The comparators’ output is ‘0011’ for each
ADC.
The SINC filters are all reset, as well as their double
output buffers. This pin is independent of the serial
interface. It brings the CONFIG registers to the default
state. When RESET is low, any write with the SPI
interface will be disabled and will have no effect. All
output pins (SDO, DR, MDAT0/1) are high-impedance,
and no clock is propagated through the chip.
5.10
The MCP3901 incorporates a phase delay generator
which ensures that the two ADCs are converting the
inputs with a fixed delay between them. The two ADCs
are synchronously sampling but the averaging of
modulator outputs is delayed. Therefore, the SINC filter
outputs (thus, the ADC outputs) show a fixed phase
delay, as determined by the PHASE register setting.
The PHASE register (PHASE<7:0>) is a 7 bit + sign,
MSB first, two’s complement register that indicates how
much phase delay there is to be between Channel 0
and Channel 1. The reference channel for the delay is
Channel 1 (typically the voltage channel for power
metering applications). When PHASE<7:0> are posi-
tive, Channel 0 is lagging versus Channel 1. When
PHASE<7:0> are negative, Channel 0 is leading
versus Channel 1. The amount of delay between two
ADC conversions is given by the following formula:
EQUATION 5-5:
The timing resolution of the phase delay is 1/DMCLK or
1 µs in the default configuration with MCLK = 4 MHz.
The data ready signals are affected by the phase delay
settings. Typically, the time difference between the data
ready pulses of Channel 0 and Channel 1 is equal to
the phase delay setting.
Note:
RESET Effect on Delta-Sigma
Modulator/SINC Filter
Phase Delay Block
Delay
A detailed explanation of the Data Ready
pin (DR) with phase delay is present in
Section 6.10 “Data Ready Latches and
Data Ready Modes
=
Phase Register Code
------------------------------------------------- -
© 2010 Microchip Technology Inc.
DMCLK
(DRMODE<1:0>)”.