DS14287 Maxim Integrated Products, DS14287 Datasheet
DS14287
Specifications of DS14287
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DS14287 Summary of contents
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... AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GND Encapsulated Package Control Control SQW CEO 4 21 CEI BAT 6 19 IRQ RESET GND R DIP/ CEI BAT DS14285 IRQ 23 7 RESET GND PLCC SQW 2 DS14287 CEO CEI N. IRQ RESET N. R REV: 112105 ...
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... SO (0.300″)/Tape & Reel 5 (0.300″)/Tape & Reel 5 (0.300″)/Tape & Reel 5.0 24 EDIP (0.740″) 5.0 24 EDIP (0.740″ TOP MARK* DS14285 DS14285 DS14285N DS14285N DS14285Q DS14285Q DS14285QN DS14285QN DS14285S DS14285S DS14285SN DS14285SN DS14285SN DS14285SN DS14285S DS14285S DS14287 DS14287 ...
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... AD0 to AD6. Valid write data must be present and held stable during the latter portion of the DS or pulses read cycle the DS14285/DS14287 outputs 8 bits of data during the latter portion of the DS or pulses. The read cycle is terminated and the bus returns to a high impedance state as DS transitions ...
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... GND, Intel bus timing is selected. In this mode the DS pin is called Read( the time period when the DS14285Q drives the bus with read data. The as the Output Enable ( ) signal on a typical memory. OE The DS14285, DS14285S and DS14287 do not have a MOT pin and therefore operate only in Intel bus timing mode. R/ (Read/Write Input) - The R/ W ...
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... RAM. On power-up the RESET is returned high. RESET ) bit is cleared to 0. SQWE can be connected This connection will allow the DS14287 CEI logic high. When V RESET . CEI provides the higher of V ...
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... The battery should be connected directly to the V battery to the VBAT pin. Furthermore, a diode is not necessary because reverse charging current protection circuitry is provided internal to the device and has passed the requirements of Underwriters Laboratories for UL listing. Figure 1. DS14285/DS14287 Block Diagram pin. A diode must not be placed in series with the BAT ...
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... When the device is in battery backup mode, the energy source connected to the V the DS14285, or the internal lithium cell in the case of the DS14287 can power an external SRAM for an extended period of time. The amount of time that the lithium cell can supply power to the external SRAM is a function of the data retention current of the SRAM ...
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... RTC ADDRESS MAP The address map of the DS14285/DS14287 is shown in Figure 2. The address map consists of 114 bytes of user RAM, 10 bytes of RAM that contain the RTC time, calendar, and alarm data, and 4 bytes which are used for control and status. All 128 bytes can be directly written or read except for the following: 1 ...
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When the 12-hour format is selected, the high order bit of the hours byte represents PM when logic one. The time, calendar, and alarm bytes are always ...
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... CONTROL REGISTERS The DS14285/DS14287 has four control registers that are accessible at all times, even during the update cycle. REGISTER A MSB BIT 7 BIT 6 UIP DV2 UIP - The Update In Progress (UIP) bit is a status flag that can be monitored. When the UIP bit the update transfer will soon occur. When UIP the update transfer will not occur for at least 244 µ ...
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... IRQ PIE bit blocks the output from being driven by a periodic interrupt, but the Periodic Flag (PF) bit is IRQ still set at the periodic rate. PIE is not modified by any internal DS14285/DS14287 functions, but is cleared RESET AIE - The Alarm Interrupt Enable (AIE) bit is a read/write bit which, when set permits the Alarm Flag (AF) bit in register C to assert equal the 3 alarm bytes including a “ ...
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REGISTER C MSB BIT 7 BIT 6 IRQF PF IRQF - The Interrupt Request Flag (IRQF) bit is set when one or more of the following are true PIE = AIE = ...
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... The DS14285/DS14287 can also provide additional nonvolatile RAM. This is accomplished through the use of its internal lithium cell in the case of the DS14287 (or the energy source connected to the V in the case of the DS14285) and battery-backup controller to make a standard CMOS SRAM nonvolatile during power-fail conditions ...
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... Determination that the RTC initiated an interrupt is IRQ accomplished by reading Register C. A logic one in bit 7 (IRQF bit) indicates that one or more interrupts have been initiated by the DS14285/DS14287. The act of reading Register C clears all active flag bits and the IRQF bit. PERIODIC INTERRUPT SELECTION The periodic interrupt will cause the every 122 µ ...
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... UPDATE CYCLE The DS14285/DS14287 executes an update cycle once per second regardless of the SET bit in Register B. When the SET bit in Register B is set to one, the user copy of the double buffered time, calendar, and alarm bytes is frozen and will not update as the time increments. However, the time countdown chain continues to update the internal copy of the buffer ...
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Figure 4. Update-Ended and Periodic Interrupt Relationship ...
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ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………………………………..-0.5V to +7.0V Storage Temperature Range………………………………………………………………...-40°C to +85°C Soldering Temperature: DIP…………………………………………..260°C for 10 seconds (See Note 12) Soldering Temperature: Surface Mount:…………………………….See IPC/JEDEC Standard J-STD-020 This is a stress rating only ...
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AC ELECTRICAL CHARACTERISTICS (Over the operating range) PARAMETER Cycle Pulse Width, DS/E Low or RD/ High Pulse Width, DS/E Low or RD/ Low Input Rise and Fall Time R/ Hold Time W R/ Setup Time Before DS/E W Chip Select ...
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Figure 5. Output Load DS14285 BUS TIMING FOR MOTOROLA INTERFACE ...
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... DS14285/DS14287 BUS TIMING FOR INTEL INTERFACE WRITE CYCLE ...
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... DS14285/DS14287 BUS TIMING FOR INTEL INTERFACE READ CYCLE DS14285/DS14287 IRQ RELEASE DELAY TIMING ...
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... A PARAMETER Expected Data Retention for DS14287 NOTE: The RTC keeps time to an accuracy of +1 minute per month during data retention time for the period of t WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery-backup mode. ...
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... CE 4mA is forced through Z CE 12) Real-Time Clock Modules such as the DS14287 can be successfully processed through conventional wave-soldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85°C. Post-solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used. ...
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PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/DallasPackInfo.) DS14285 24-PIN DIP DS14285 24-PIN SO PKG 24-PIN DIM MIN MAX A IN. 1.245 1.270 ...
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PACKAGE INFORMATION (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/DallasPackInfo.) DS14285Q 28-PIN PLCC PKG DIM ...
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... PACKAGE INFORMATION (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/DallasPackInfo.) DS14287 REAL-TIME CLOCK PLUS RAM PKG DIM MIN A IN. 1.320 MM 33.53 B IN. 0.720 MM 18.29 C IN. 0.345 MM 8.76 D IN. ...