X1227S8-2.7A Intersil, X1227S8-2.7A Datasheet
X1227S8-2.7A
Specifications of X1227S8-2.7A
Related parts for X1227S8-2.7A
X1227S8-2.7A Summary of contents
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... Watchdog Low Voltage Timer Reset CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc Trademark of Philips. All other trademarks mentioned are the property of their respective owners. X1227 FN8099.2 Battery ...
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... X1227S8* X1227 X1227S8Z* (Note 1) X1227Z X1227S8I X1227I X1227S8IZ (Note 1) X1227ZI X1227V8 1227 X1227V8Z (Note 1) 1227Z X1227V8I 1227I X1227V8IZ (Note 1) 1227IZ X1227S8-2.7A X1227AN X1227S8Z-2.7A (Note 1) X1227ZAN X1227S8I-2.7A* X1227AP X1227S8IZ-2.7A* (Note 1) X1227ZAP X1227V8-2.7A 1227AN X1227V8Z-2.7A (Note 1) 1227ANZ X1227V8I-2.7A 1227AP X1227V8IZ-2.7A (Note 1) 1227APZ X1227S8-2.7* X1227F X1227S8Z-2 ...
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PIN DESCRIPTIONS X1 X2 RESET internal connection PIN ASSIGNMENTS Pin Number SOIC TSSOP Symbol RESET SDA 6 8 SCL 7 1 ...
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ABSOLUTE MAXIMUM RATINGS Temperature Under Bias ................... -65°C to +135°C Storage Temperature ........................ -65°C to +150°C Voltage pin CC BACK (respect to ground)...............................-0.5V to 7.0V Voltage on SCL, SDA, X1 and X2 pin (respect to ground) ...
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Others = GND or V SDA SCL BACK (10)V = GND GND or V SDA CC SCL (11)I = 3.0mA at 5.5V, 1.5mA at 2.7V OL (12 -1.0mA ...
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AC Specifications (T = -40°C to +85°C, VCC = +2.7V to +5.5V, unless otherwise specified.) A Symbol f SCL Clock Frequency SCL t Pulse width Suppression Time at inputs IN t SCL LOW to SDA Data Out Valid AA t ...
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Write Cycle Timing SCL 8th Bit of Last Byte SDA Power-up Timing Symbol (1) t Time from Power-up to Read PUR (1) t Time from Power-up to Write PUW Notes: (1) Delays are measured from the time V sampled and ...
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V Programming Timing Diagram TRIP TRIP RESET VPS SCL SDA AEh V Programming Parameters TRIP Parameter t V Program Enable Voltage Setup time VPS TRIP ...
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DESCRIPTION (continued) The Real-Time Clock keeps track of time with separate registers for Hours, Minutes, Seconds. The Calendar has separate registers for Date, Month, Year and Day-of-week. The calendar is correct through 2099, with automatic leap year correction. The powerful ...
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... For example, a >20ppm frequency deviation translates into an accuracy of >1 minute per month. These parameters are available from the crystal manufacturer. Intersil’s RTC family provides on-chip crystal compensation networks to adjust load- capacitance to tune oscillator frequency from +116 ppm to -37 ppm when using a 12.5 pF load crystal. For more detail information see the Application section ...
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A read or write can begin at any address in the CCR not necessary to set the RWEL bit ...
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When there is a match, an alarm flag is set. The occur- rence of an alarm can be determined by polling the AL0 and AL1 bits or by enabling the IRQ output, using it as hardware flag. The alarm enable ...
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The bit is set regardless of whether V applied first. The loss of only one of the supplies does not set the RTCF bit to “1”. On power-up after a total power failure, all registers are set to their default ...
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... ATR value. See Application section and Intersil’s Application Note AN154 for more information. WRITING TO THE CLOCK/CONTROL REGISTERS Changing any of the nonvolatile bits of the clock/con- trol register requires the following steps: – ...
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POWER-ON RESET Application of power to the X1227 activates a Power- on Reset Circuit that pulls the RESET pin active. This signal provides several benefits. – It prevents the system microprocessor from starting to operate with insufficient voltage. – It ...
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Figure 5. Power-on Reset and Low Voltage Reset V TRIP PURST t R RESET V THRESHOLD RESET PROCEDURE CC [OPTIONAL] The X1227 is shipped with a standard voltage. This value will not change over ...
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Figure 7. Reset V Level Sequence TRIP RESET SCL SDA AEh Note: BP0, BP1, BP2 must be disabled. SERIAL COMMUNICATION Interface Conventions The device supports a bidirectional bus oriented proto- ...
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Figure 8. Valid Data Changes on the SDA Bus SCL SDA Figure 9. Valid Start and Stop Conditions SCL SDA Figure 10. Acknowledge Response From Receiver SCL from Master Data Output from Transmitter Data Output from Receiver DEVICE ADDRESSING Following ...
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Figure 11. Slave Address, Word Address, and Data Bytes (64 Byte pages) Device Identifier Array CCR Write Operations Byte Write For a write operation, the device requires the Slave Address ...
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Page Write The X1227 has a page write operation initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit up ...
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Acknowledge Polling Disabling of the inputs during nonvolatile write cycles can be used to take advantage of the typical 5mS write cycle time. Once the stop condition is issued to indi- cate the end of the master’s byte load operation, ...
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Random Read Random read operations allows the master to access any location in the X1227. Prior to issuing the Slave Address Byte with the R/W bit set to zero, the master must first perform a “dummy” write operation. The master ...
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... In addition to the analog compensation afforded by the adjustable load capacitance, a digital compensation feature is available for the Intersil RTC family. There are three bits known as the Digital Trimming Register or DTR, and they operate by adding or skipping pulses in the clock signal. The range provided is ±30ppm in increments of 10ppm ...
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... RTC circuit is to power it up and read the real time clock as time advances. Backup Battery Operation Many types of batteries can be used with the Intersil RTC products. 3.0V or 3.6V Lithium batteries are appropriate, and sizes are available that can power a Intersil RTC device for years. Another option is to use a supercapacitor for applications where Vcc may disappear intermittently for short periods of time ...
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Figure 20. Supercapacitor charging circuit 2.7-5. back V SS Since the battery switchover occurs at Vcc=Vback- 0.1V (see Figure 20), the battery voltage must always Table 8. ...
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Referring to Figure 20, Vtrip applies to the “Internal Vcc” node which powers the entire device. This means that if Vcc is powered down and the battery voltage at Vback is higher than the Vtrip voltage, then the entire chip ...
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Small Outline Package Family (SO PIN #1 I.D. MARK 0.010 SEATING PLANE 0.004 C 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...