DS1747P-70+ Maxim Integrated Products, DS1747P-70+ Datasheet - Page 6

• Manufacturer Part Number: DS1747P-70+
• Description: IC RTC RAM Y2K 5V 70NS 34-PCM
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/NVSRAM/Y2Kr

Specifications of DS1747P-70+

• Memory Size: 4M (512K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 34-PowerCap™ Module
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NOTE: All indicated “X” bits are unused, but must be set to “0” during write cycles to ensure proper clock operation.
Table 2. Register Map
OSC = Stop Bit
W = Write Bit
RETRIEVING DATA FROM RAM OR CLOCK
The DS1747 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE
(chip enable) is low. The device architecture allows ripple-through access to any of the address locations
in the NV SRAM. Valid data will be available at the DQ pins within t
stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times and
states are not met, valid data will be available at the latter of chip-enable access (t
access time (t
outputs are activated before t
inputs are changed while CE and OE remain valid, output data will remain valid for output data hold
time (t
WRITING DATA TO RAM OR CLOCK
The DS1747 is in the write mode whenever WE, and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE. The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of t
write cycle. Data in must be valid t
typical application, the OE signal will be high during a write cycle. However, OE can be active provided
that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low
the data bus can become active with read data defined by the address inputs. A low transition on WE
will then disable the output t
ADDRESS
7FFFD
7FFFC
7FFFF
7FFFE
7FFFB
7FFFA
7FFF9
7FFF8
OH
) but will then go indeterminate until the next address access.
OSC
OEA
B7
BF
W
X
X
X
X
)
. The state of the data input/output pins (DQ) is controlled by CE and OE. If the
B6
FT
X
X
X
R
10 Year
R = Read Bit
X = See Note
WEZ
AA
10 Seconds
10 Minutes
, the data lines are driven to an intermediate state until t
after WE goes active.
B5
X
X
10 Century
10 Hour
10 Date
DS
prior to the end of write and remain valid for t
10 Month
B4
X
DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
DATA
6 of 16
B3
X
B2
WR
Seconds
FT = Frequency Test
BF = Battery Flag
Minutes
Century
prior to the initiation of another read or
Month
Year
Date
Hour
Day
B1
AA
after the last address input is
B0
CEA
)
or at output enable
DH
FUNCTION
AA.
Seconds
Minutes
Century
Month
afterward. In a
Year
Date
Hour
Day
If the address
RANGE
00-59
00-99
01-12
01-31
01-07
00-23
00-59
00-39