DS1644-120+ Maxim Integrated Products, DS1644-120+ Datasheet - Page 5

• Manufacturer Part Number: DS1644-120+
• Description: IC RAM TIMEKEEP NV 120NS 28-EDIP
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/NVSRAMr

Specifications of DS1644-120+

• Memory Size: 256K (32K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 28-DIP Module (600 mil), 28-EDIP
• Function: Clock/Calendar/NV Timekeeping RAM
• Rtc Memory Size: 32768 Byte
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Rtc Bus Interface: Parallel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS1644 REGISTER MAP—BANK1 Table 2
OSC = STOP BIT
W = WRITE BIT
Note: All indicated “X” bits are unused but must be set to “0” during write cycles to ensure proper clock
operation.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1644 is in the read mode whenever
device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid
data will be available at the DQ pins within t
and
available at the latter of chip enable access (t
data input/output pins (DQ) is controlled by
lines are driven to an intermediate state until t
remain valid, output data will remain valid for output data hold time (t
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1644 is in the write mode whenever
referenced to the latter occurring high to low transition of
throughout the cycle.
another read or write cycle. Data in must be valid t
afterward. In a typical application, the
active provided that care is taken with the data bus to avoid bus contention. If
transitioning low the data bus can become active with read data defined by the address inputs. A low
transition on
ADDRESS
7FFD
7FFA
7FFC
7FFB
7FFF
7FFE
7FF9
7FF8
OE
access times and states are satisfied. If
WE
OSC
B
—
W
X
X
X
X
X
will then disable the outputs t
7
R = READ BIT
X = UNUSED
CE
FT
B
—
—
—
X
X
X
R
6
or
WE
B
—
—
—
—
X
X
X
-
5
must return inactive for a minimum of t
FT = FREQUENCY TEST
OE
B
—
—
—
—
—
—
X
X
signal will be high during a write cycle. However,
DATA
4
WE
AA
CE
WE
CEA
WEZ
after the last address input is stable, providing that the
AA
(write enable) is high, and
) or at output enable access time (t
and
CE
5 of 14
. If the address inputs are changed while
and
B
—
—
—
—
—
—
X
X
after
3
DS
or
OE
CE
prior to the end of write and remain valid for t
OE
WE
. If the outputs are activated before t
B
—
—
—
—
—
—
—
are in their active state. The start of a write is
X
WE
2
access times are not met, valid data will be
goes active.
or
CE
B
—
—
—
—
—
—
—
X
1
. The addresses must be held valid
OH
) but will then go indeterminate
B
—
—
—
—
—
—
—
X
CE
WR
0
(chip enable) is low. The
prior to the initiation of
OE
Seconds
Minutes
Control
Month
OEA
Hour
Year
Date
Day
is low prior to
FUNCTION
). The state of the
DS1644/DS1644P
CE
AA
OE
, the data
00-99
01-12
01-31
01-07
00-23
00-59
00-59
and
A
can be
WE
CE
OE
DH