DS1340U-33+T&R Maxim Integrated Products, DS1340U-33+T&R Datasheet - Page 4

• Manufacturer Part Number: DS1340U-33+T&R
• Description: IC RTC I2C W/CHARGER 3.3V 8-USOP
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/Trickle-Chargerr

Specifications of DS1340U-33+T&R

• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.97 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -

I
POWER-UP/POWER-DOWN CHARACTERISTICS
(T
4
WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery-backup mode.
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
Note 17:
Figure 1. Data Transfer on I
Recovery at Power-Up
V
V
V
V
2
A
CC
PF(MIN)
CC
PF(MAX)
SDA
SCL
NOTE: TIMING IS REFERENCED TO V
= -40°C to +85°C) (Figure 2)
C RTC with Trickle Charger
_____________________________________________________________________
Fall Time; V
Rise Time; V
STOP
PARAMETER
Limits at -40°C are guaranteed by design and not production tested.
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the V
signal) to bridge the undefined region of the falling edge of SCL.
The maximum t
A fast-mode device can be used in a standard-mode system, but the requirement t
is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the
low period of the SCL signal, it must output the next data bit to the SDA line t
before the SCL line is released.
C
The parameter t
V
All voltages are referenced to ground.
Measured at V
The use of the 250Ω trickle-charge resistor is not allowed at V
Measured at V
Measured at V
I
Specified with I
Measured with a 32.768kHz crystal attached to the X1 and X2 pins.
Limits at +25°C are guaranteed by design and not production tested.
This delay applies only if the oscillator is enabled and running. If the oscillator is disabled or stopped, no power-up delay
occurs.
CCA
CCMAX
t
B
BUF
—total capacitance of one bus line in pF.
—SCL clocking at max frequency = 400kHz.
START
PF(MAX)
PF(MIN)
and 1.3V ≤ V
t
HD:STA
to
to
IL(MAX)
CC
CC
CC
HD:DAT
2
OSF
2
C bus inactive.
t
LOW
C Serial Bus
= typ, V
= typ, V
= typ, V
AND V
is the period of time the oscillator must be stopped for the OSF flag to be set over the 0V ≤ V
BAT
IH(MIN)
only has to be met if the device does not stretch the low period (t
t
R
SYMBOL
BACKUP
BACKUP
BACKUP
≤ 3.7V range.
.
t
t
t
VCCR
VCCF
REC
t
HD:DAT
= 0V, register 08h = A5h.
= 0V, register 08h = A6h.
= 0V, register 08h = A7h.
(Note 17)
t
HIGH
t
F
t
SU:DAT
CONDITIONS
REPEATED
START
CC
> 3.63V and should not be enabled.
t
SU:STA
t
HD:STA
R MAX
SU:DAT
+ t
SU:DAT
MIN
300
0
LOW
≥ to 250ns must be met. This
) of the SCL signal.
= 1000 + 250 = 1250ns
t
SP
TYP
IH(MIN)
MAX
t
SU:STO
2
of the SCL
CC
UNITS
ms
µs
µs
≤