ISL12029IBZ Intersil, ISL12029IBZ Datasheet - Page 19

• Manufacturer Part Number: ISL12029IBZ
• Description: IC RTC W/EEPROM 14-SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/Supervisor/EEPROMr

Specifications of ISL12029IBZ

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In the read mode, the device will transmit 8 bits of data,
release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the device will continue
to transmit data. The device will terminate further data
transmissions if an acknowledge is not detected. The master
must then issue a stop condition to return the device to
Standby mode and place the device into a known state.
Device Addressing
Following a start condition, the master must output a Slave
Address Byte. The first 4 bits of the Slave Address Byte
specify access to either the EEPROM array or to the CCR.
Slave bits ‘1010’ access the EEPROM array. Slave bits
‘1101’ access the CCR.
When shipped from the factory, EEPROM array is
UNDEFINED, and should be programmed by the customer
to a known state.
Bit 3 through Bit 1 of the slave byte specify the device select
bits. These are set to ‘111’.
ARRAY
CCR
FIGURE 19. SLAVE ADDRESS, WORD ADDRESS, AND DATA BYTES (64 BYTE PAGES)
A7
D7
1
1
0
19
DEVICE IDENTIFIER
A6
D6
0
1
0
A5
D5
1
0
0
ISL12029, ISL12029A
A4
D4
0
1
0
A3
D3
1
0
A2
D2
1
0
The last bit of the Slave Address Byte defines the operation
to be performed. When this R/W bit is a one, then a read
operation is selected. A zero selects a write operation (refer
to Figure 19).
After loading the entire Slave Address Byte from the SDA bus,
the ISL12029 compares the device identifier and device select
bits with ‘1010111’ or ‘1101111’. Upon a correct compare, the
device outputs an acknowledge on the SDA line.
Following the Slave Byte is a two byte word address. The
word address is either supplied by the master device or
obtained from an internal counter. On power-up the internal
address counter is set to address 0h, so a current address
read of the EEPROM array starts at address 0. When
required, as part of a random read, the master must supply
the 2 Word Address Bytes as shown in Figure 19.
In a random read operation, the slave byte in the “dummy
write” portion must match the slave byte in the “read”
section. That is if the random read is from the array the slave
byte must be 1010111x in both instances. Similarly, for a
random read of the Clock/Control Registers, the slave byte
must be 1101111x in both places.
A1
D1
1
0
R/W
A8
A0
D0
SLAVE ADDRESS BYTE
WORD ADDRESS 1
WORD ADDRESS 0
DATA BYTE
BYTE 0
BYTE 3
BYTE 1
BYTE 2
December 16, 2010
FN6206.10