DS1746-70+ Maxim Integrated Products, DS1746-70+ Datasheet - Page 6

• Manufacturer Part Number: DS1746-70+
• Description: IC RTC RAM Y2K 5V 70NS 32-EDIP
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/NVSRAM/Y2Kr

Specifications of DS1746-70+

• Memory Size: 1M (128K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 32-DIP Module (600 mil), 32-EDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2. Register Map
Note: All indicated “X” bits are not used but must be set to “0” during a write cycle to ensure proper clock
operation.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1746 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE
(chip enable) is low. The device architecture allows ripple-through access to any of the address locations
in the NV SRAM. Valid data will be available at the DQ pins within t
stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times and
states are not met, valid data will be available at the latter of chip enable access (t
access time (t
are activated before t
are changed while CE and OE remain valid, output data will remain valid for output data hold time (t
but will then go indeterminate until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1746 is in the write mode whenever WE, and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE, or CE. The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of t
write cycle. Data in must be valid t
typical application, the OE signal will be high during a write cycle. However, OE can be active provided
that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low the
data bus can become active with read data defined by the address inputs. A low transition on WE will
then disable the output t
OSC = Stop Bit
W = Write Bit
ADDRESS
1FFFD
1FFFC
1FFFF
1FFFE
1FFFB
1FFFA
1FFF9
1FFF8
OEA
OSC
B7
BF
W
X
X
X
X
)
. The state of the data input/output pins (DQ) is controlled by CE and OE. If the outputs
AA
, the data lines are driven to an intermediate state until t
WEZ
B6
FT
R
X
X
X
10 Year
R = Read Bit
X = See Note
after WE goes active.
10 Seconds
10 Minutes
B5
X
X
10 Century
10 Date
10 Hour
DS
prior to the end of write and remain valid for t
10 Month
B4
X
DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs
DATA
6 of 16
B3
X
B2
WR
Seconds
FT = Frequency Test
BF = Battery Flag
Minutes
Century
Month
Year
Date
Hour
prior to the initiation of another read or
Day
B1
AA
after the last address input is
B0
AA
CEA
. If the address inputs
)
or at output enable
FUNCTION
DS
Seconds
Minutes
Century
Month
Hour
Year
Date
afterward. In a
Day
RANGE
00-99
01-12
01-31
01-07
00-23
00-59
00-59
00-39
OH
)