DS1743WP-120IND+ Maxim Integrated Products, DS1743WP-120IND+ Datasheet - Page 6

• Manufacturer Part Number: DS1743WP-120IND+
• Description: IC RTC RAM Y2K 3.3V 120NS 34-PCM
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/NVSRAM/Y2Kr

Specifications of DS1743WP-120IND+

• Memory Size: 64K (8K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 34-PowerCap™ Module
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CLOCK ACCURACY (DIP MODULE)
The DS1743 is guaranteed to keep time accuracy to within 1 minute per month at +25C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not require
additional calibration. For this reason, methods of field clock calibration are not available and not
necessary. The electrical environment also affects clock accuracy, so caution should be taken to place the
RTC in the lowest-level EMI section of the PC board layout. For additional information, please refer to
Application Note 58: Crystal Considerations with Dallas Real-Time Clocks.
CLOCK ACCURACY (PowerCap MODULE)
The DS1743 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within 1.53 minutes per month (35ppm) at +25°C. The
electrical environment also affects clock accuracy, so caution should be taken to place the RTC in the
lowest-level EMI section of the PC board layout. For additional information, please refer to Application
Note 58: Crystal Considerations with Dallas Real-Time Clocks.
Table 2. Register Map
RETRIEVING DATA FROM RAM OR CLOCK
The DS1743 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE
(chip enable) is low. The device architecture allows ripple-through access to any of the address locations in
the NV SRAM. Valid data will be available at the DQ pins within t
providing that the, CE and OE access times and states are satisfied. If CE, or OE access times and states
are not met, valid data will be available at the latter of chip enable access (t
time (t
activated before t
changed while CE and OE remain valid, output data will remain valid for output data hold time (t
will then go indeterminate until the next address access.
ADDRESS
OSC = STOP BIT
W = WRITE BIT
Note: All indicated “X” bits must be set to “0” when written to ensure proper clock operation.
1FFD
1FFA
1FFE
1FFC
1FFB
1FFF
1FF9
1FF8
CEA
). The state of the data input/output pins (DQ) is controlled by CE and OE. If the outputs are
OSC
BF
B
W
X
X
X
X
7
AA
R = READ BIT
X = SEE NOTE BELOW
, the data lines are driven to an intermediate state until t
FT
B
X
X
X
R
6
10 Year
10 Minutes
10 Seconds
B
X
X
10 Century
5
10 Hour
10 Date
Month
DATA
B
10
X
FT = FREQUENCY TEST
BF = BATTERY FLAG
4
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
B
X
3
6 of 16
Seconds
Minutes
Century
B
Month
Hour
Year
Date
2
Day
B
1
AA
B
after the last address input is stable,
0
CEA
FUNCTION
AA
Minutes
Seconds
Control
) or at output enable access
Month
Hour
Year
Date
. If the address inputs are
Day
RANGE
00–99
01–12
01–31
01–07
00–23
00–59
00–59
00–39
OH
) but