DS1672-33+ Maxim Integrated Products, DS1672-33+ Datasheet - Page 12

• Manufacturer Part Number: DS1672-33+
• Description: IC TIMEKEEPER 3.3V 32-BIT 8-DIP
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/Trickle-Chargerr

Specifications of DS1672-33+

• Time Format: Binary
• Date Format: Binary
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Function: Clock/Calendar/Elapsed Time Counter
• Supply Voltage (max): 3.63 V
• Supply Voltage (min): 2.97 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: Through Hole
• Rtc Bus Interface: Serial (I2C)
• Supply Current: 600 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

I
The DS1672 supports a bidirectional I
onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that controls
the message is called a master. The devices that are controlled by the master are slaves. The bus must be
controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates
the START and STOP conditions. The DS1672 operates as a slave on the I
are made via the open-drain I/O lines SDA and SCL. Within the bus specifications, a standard mode
(100kHz maximum clock rate) and a fast mode (400kHz maximum clock rate) are defined. The DS1672
operates in both modes.
The following bus protocol has been defined (Figure 6):
 Data transfer may be initiated only when the bus is not busy.
 During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in
Accordingly, the following bus conditions have been defined:
2
C Serial Data Bus
the data line while the clock line is high will be interpreted as control signals.
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line from high to low, while the clock line is
high, defines a START condition.
Stop data transfer: A change in the state of the data line from low to high, while the clock line is
high, defines a STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the
data line is stable for the duration of the high period of the clock signal. The data on the line must
be changed during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition.
The number of data bytes transferred between the START and the STOP conditions is not limited,
and is determined by the master device. The information is transferred byte-wise and each
receiver acknowledges with a ninth bit. Within the I
(100kHz clock rate) and a fast mode (400kHz clock rate) are defined.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge
after the reception of each byte. The master device must generate an extra clock pulse that is
associated with this acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in
such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related
clock pulse. Of course, setup and hold times must be taken into account. A master must signal an
end of data to the slave by not generating an acknowledge bit on the last byte that has been
clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master
to generate the STOP condition.
2
C bus and data transmission protocol. A device that sends data
12 of 15
2
C bus specifications a standard mode
2
C bus. Connections to the bus