ISL1209IU10Z Intersil, ISL1209IU10Z Datasheet - Page 14

IC RTC LP BATT BACK SRAM 10MSOP

ISL1209IU10Z

Manufacturer Part Number
ISL1209IU10Z
Description
IC RTC LP BATT BACK SRAM 10MSOP
Manufacturer
Intersil
Type
Clock/Calendar/NVSRAMr
Datasheet

Specifications of ISL1209IU10Z

Memory Size
2B
Time Format
HH:MM:SS (12/24 hr)
Date Format
YY-MM-DD-dd
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
10-MSOP, Micro10™, 10-uMAX, 10-uSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISL1209IU10Z-TK
Manufacturer:
Intersil
Quantity:
47 631
Part Number:
ISL1209IU10Z-TK
Manufacturer:
Intersil
Quantity:
625
AUTO RESET ENABLE BIT (ARST)
This bit enables/disables the automatic reset of the BAT and
ALM status bits only. When ARST bit is set to “1”, these
status bits are reset to “0” after a valid read of the respective
status register (with a valid STOP condition). When the
ARST is cleared to “0”, the user must manually reset the
BAT and ALM bits.
INTERRUPT CONTROL REGISTER (INT)
FREQUENCY OUT CONTROL BITS (FO <3:0>)
These bits enable/disable the frequency output function and
select the output frequency at the IRQ/F
Table 8 for frequency selection. When the frequency mode is
enabled, it will override the alarm mode at the IRQ/F
FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB)
This bit enables/disables the F
backup mode (i.e. V
FOBATB is set to “1” the F
battery backup mode. This means that both the frequency
output and alarm output functions are disabled. When the
FOBATB is cleared to “0”, the F
during battery backup mode.
08h
Default
FREQUENCY,
ADDR
32768
F
4096
1024
1/16
1/32
1/2
1/4
1/8
OUT
TABLE 7. INTERRUPT CONTROL REGISTER (INT)
64
32
16
TABLE 8. FREQUENCY SELECTION OF F
0
8
4
2
1
IM ALME LPMODE FOBATB FO3 FO2 FO1 FO0
7
0
6
0
UNITS
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
BAT
5
0
power source active). When the
FO3
OUT
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
14
OUT
/IRQ pin is disabled during
OUT
4
0
/IRQ pin during battery
/IRQ pin is enabled
FO2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
OUT
3
0
pin. See
FO1
OUT
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
2
0
PIN
OUT
1
0
FO0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
pin.
0
0
ISL1209
LOW POWER MODE BIT (LPMODE)
This bit enables/disables low power mode. With
LPMODE = “0”, the device will be in normal mode and the
V
V
power mode and the V
V
about 600nA when using LPMODE = “1” with V
(See Typical Performance Curves: I
LPMODE ON & OFF.)
ALARM ENABLE BIT (ALME)
This bit enables/disables the alarm function. When the ALME
bit is set to “1”, the alarm function is enabled. When the ALME
is cleared to “0”, the alarm function is disabled. The alarm
function can operate in either a single event alarm or a periodic
interrupt alarm (see IM bit).
NOTE: When the frequency output mode is enabled, the alarm function
is disabled.
INTERRUPT/ALARM MODE BIT (IM)
This bit enables/disables the interrupt mode of the alarm
function. When the IM bit is set to “1”, the alarm will operate
in the interrupt mode, where an active low pulse width of
250ms will appear at the IRQ/F
triggered by the alarm as defined by the alarm registers (0Ch
to 11h). When the IM bit is cleared to “0”, the alarm will
operate in standard mode, where the IRQ/F
tied low until the ALM status bit is cleared to “0”.
EVENT DETECTION REGISTER (EV)
The ISL1209 provides an easy to use event and tamper
detection circuit. The Event Detection Register configures
the functionality of the event detection circuits.
EVENT INPUT SAMPLING SELECTION BITS
(ESMP<1:0>)
These two bits select the rate of sampling of the EVIN pin to
trigger an event detection. For example, a 2Hz sampling rate
would configure the ISL1209 to check the status of the EV
pin twice a second. Slower sampling significantly reduces
the supply current drain.
BAT
DD
DD
ESMP1
< V
< V
supply will be used when V
IM BIT
0
0
1
1
TRIP
0
1
BAT
. With LPMODE = “1”, the device will be in low
- V
BATHYS
Single Time Event Set By Alarm
Repetitive/Recurring Time Event Set By Alarm
ESMP0
BAT
0
1
0
1
INTERRUPT/ALARM FREQUENCY
. There is a supply current saving of
TABLE 10.
TABLE 9.
supply will be used when
OUT
DD
EVENT SAMPLING RATE
DD
pin when the RTC is
< V
vs VDD with
BAT
Always ON
1
OUT
2Hz
1Hz
/
- V
4
Hz
DD
BATHYS
October 17, 2006
pin will be
= 5V.
FN6109.4
and

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