ISL1208IB8Z Intersil, ISL1208IB8Z Datasheet - Page 5

• Manufacturer Part Number: ISL1208IB8Z
• Description: IC RTC LP BATT BACKED SRAM 8SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/NVSRAMr

Specifications of ISL1208IB8Z

• Memory Size: 2B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Interface Specifications
NOTES:
10. Parameter is not 100% tested.
11. These are I
5. IRQ and F
6. LPMODE = 0 (default).
7. In order to ensure proper timekeeping, the V
8. Typical values are for T = +25°C and 3.3V supply voltage.
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
Hysteresis SDA and SCL Input Buffer
SYMBOL
t
t
t
t
t
t
HD:STO
HD:STA
SU:DAT
HD:DAT
SU:STO
SU:STA
t
C
t
t
and are not production tested.
f
HIGH
V
LOW
Rpu
V
SCL
t
BUF
t
t
Cb
DH
AA
t
PIN
t
IN
OL
R
F
IH
SDA and SCL Input Buffer HIGH
Voltage
Hysteresis
SDA Output Buffer LOW Voltage,
Sinking 3mA
SDA and SCL Pin Capacitance
SCL Frequency
Pulse width Suppression Time at
SDA and SCL Inputs
SCL Falling Edge to SDA Output
Data Valid
Time the Bus Must Be Free Before
the Start of a New Transmission
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
START Condition Hold Time
Input Data Setup Time
Input Data Hold Time
STOP Condition Setup Time
STOP Condition Hold Time
Output Data Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive Loading of SDA or SCL Total on-chip and off-chip
SDA and SCL Bus Pull-Up
Resistor Off-Chip
OUT
2
C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification.
Inactive.
PARAMETER
5
Over the recommended operating conditions unless otherwise specified. (Continued)
DD SR-
T
V
Any pulse narrower than the max spec is
suppressed.
SCL falling edge crossing 30% of V
SDA exits the 30% to 70% of V
SDA crossing 70% of V
condition, to SDA crossing 70% of V
during the following START condition.
Measured at the 30% of V
Measured at the 70% of V
SCL rising edge to SDA falling edge. Both
crossing 70% of V
From SDA falling edge crossing 30% of V
to SCL falling edge crossing 70% of V
From SDA exiting the 30% to 70% of V
window, to SCL rising edge crossing 30% of
V
From SCL falling edge crossing 30% of V
to SDA entering the 30% to 70% of V
window.
From SCL rising edge crossing 70% of V
to SDA rising edge crossing 30% of V
From SDA rising edge to SCL falling edge.
Both crossing 70% of V
From SCL falling edge crossing 30% of V
until SDA enters the 30% to 70% of V
window.
From 30% to 70% of V
From 70% to 30% of V
Maximum is determined by t
For Cb = 400pF, max is about 2kΩ to~2.5kΩ.
For Cb = 40pF, max is about 15kΩ to ~20kΩ
A
OUT
DD
= +25°C, f = 1MHz, V
specification must be followed.
= 0V
TEST CONDITIONS
ISL1208
DD
.
DD
DD
DD
DD
DD
DD
DD
.
during a STOP
= 5V, V
R
crossing.
crossing.
and t
DD
window.
DD
F
IN
DD
.
DD
DD
DD
, until
DD
= 0V,
DD
DD
DD
DD
DD
.
.
,
,
NOTES
10, 11
10, 11
10, 11
10, 11
10, 11
0.1 x Cb
0.1 x Cb
(Note 9)
0.05 x
1300
1300
0.7 x
V
V
20 +
20 +
MIN
600
600
600
100
600
600
20
10
DD
DD
0
0
1
(Note 8)
TYP
(Note 9)
V
MAX
400
900
900
300
300
400
DD
0.3
0.4
10
50
September 12, 2008
+
UNITS
FN8085.8
kHz
kΩ
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
V
V
V