CY25701FJXC Cypress Semiconductor Corp, CY25701FJXC Datasheet - Page 3

• Manufacturer Part Number: CY25701FJXC
• Description: IC XTAL OSC PROG SS 4-JE
• Manufacturer: Cypress Semiconductor Corp
• Type: Oscillator, Crystalr

Specifications of CY25701FJXC

• Frequency: 166MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 4-JE
• For Use With: CY3724 - SOCKET ADAPTER FOR CY25701CY3613 - PROGRAM ADAPTER CY25701FJXC428-1918 - KIT DEV FTG PROGRAMMING KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Count: -

Document #: 38-07684 Rev. *E
Absolute Maximum Rating
Supply Voltage (VDD) .................................... –0.5V to +7.0V
DC Input Voltage....................................–0.5V to V
Operating Conditions
DC Electrical Characteristics
AC Electrical Characteristics
V
T
C
F
F
T
I
I
V
V
I
I
I
C
I
∆f
DC
t
t
T
T
T
T
Notes:
Parameter
Parameter
Parameter
OH
OL
IH
IL
OZ
VDD
R
F
2. Guaranteed by characterization, not 100% tested.
3. Jitter is configuration dependent. Actual jitter is dependent on output frequencies, spread percentage, temperature, and output load. For more information, refer
A
SSCLK
MOD
PU
CCJ1
OE1
OE2
LOCK
DD
IH
IL
LOAD
IN
to the application note, “Jitter in PLL Based Systems: Causes, Effects, and Solutions” available at http://www.cypress.com/clock/appnotes.html, or contact your
local Cypress Field Application Engineer.
[2]
[3]
Output Duty Cycle
Output Rise Time
Output Fall Time
Cycle-to-Cycle Jitter SSCLK
(Pin 3)
Output Disable Time (pin1 = OE) Time from falling edge on OE to stopped
Output Enable Time (pin1 = OE) Time from rising edge on OE to outputs at a
PLL Lock Time
Output High Current (pin 3)
Output Low Current (pin 3)
Input High Voltage (pin 1)
Input Low Voltage (pin 1)
Input High Current (pin 1)
Input Low Current (pin 1)
Output Leakage Current (pin 3) Three-state output, OE = 0
Input Capacitance (pin 1)
Supply Current
Aging
Supply Voltage
Ambient Temperature
Max. Load Capacitance @ pin 3
SSCLK output frequency, C
Spread Spectrum Modulation Frequency
Power-up time for VDD to reach minimum specified voltage (power ramp must
be monotonic)
Description
Description
[2]
LOAD
SSCLK, Measured at V
20%–80% of V
20%–80% of V
SSCLK ≥133 MHz, Measured at V
25 MHz ≤ SSCLK <133 MHz, Measured at
V
SSCLK < 25 MHz, Measured at V
outputs (Asynchronous)
valid frequency (Asynchronous)
Time for SSCLK to reach valid frequency
Description
= 15 pF
V
V
CMOS levels, 70% of V
CMOS levels, 30% of V
V
V
Pin 1, or OE
V
= 0, OE = V
T
DD
A
OH
OL
in
in
DD
= 25°C, First year
/2
= V
= V
DD
= 0.5, V
= 3.3V, SSCLK = 10 to 166 MHz, C
= V
+ 0.5V
DD
SS
DD
– 0.5, V
DD
DD
DD,
DD,
= 3.3V (sink)
Condition
Condition
C
C
Storage Temperature (Non-condensing) .... –55°C to +100°C
Junction Temperature ................................ –40°C to +125°C
Data Retention @ Tj = 125°C................................> 10 years
Package Power Dissipation...................................... 350 mW
DD
L
L
= 15 pF
= 15 pF
= 3.3V (source)
DD
DD
DD
/2
DD
DD
/2
/2
LOAD
0.7V
CY25701JXC/FJXC
Min.
3.00
30.0
0.05
–20
Min.
Min.
V
–10
10
10
10
–5
–
45
–
–
–
–
SS
–
–
–
–
–
–
–
–
DD
Typ.
3.30
31.5
Typ.
Typ.
–
215
150
150
–
–
–
12
12
50
85
–
–
–
–
–
5
–
–
–
–
–
–
Max.
1/SSCK
3.60
33.0
166
500
0.3V
1% of
70
15
Max.
Max.
V
200
400
350
350
2.7
2.7
55
10
10
10
50
10
–
–
7
5
DD
Page 3 of 7
DD
MHz
Unit
kHz
ms
pF
°C
V
ppm
Unit
Unit
mA
mA
mA
µA
µA
µA
pF
ms
ns
ns
ps
ps
ns
ns
%
V
V
s
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