SI4122G-BM Silicon Laboratories Inc, SI4122G-BM Datasheet - Page 18

• Manufacturer Part Number: SI4122G-BM
• Description: IC SYNTHESIZER GSM RF2/IF 28MLP
• Manufacturer: Silicon Laboratories Inc
• Type: Frequency Synthesizerr

Specifications of SI4122G-BM

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 1.5GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Frequency-max: 1.5GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 336-1105

Si4133G
The IF output level is dependent upon the load.
Figure 18 displays the output level versus load
resistance for a variety of output frequencies.
For resistive loads greater than 500 Ω the output level
saturates and the bias currents in the IF output amplifier
are higher than needed. The LPWR bit in the Main
Configuration register (Register 0) can be set to 1 to
reduce the bias currents and therefore reduce the
power dissipated by the IF amplifier. For loads less than
500 Ω LPWR should be set to 0 to maximize the output
level.
18
Figure 18. Typical IF Output Voltage vs. Load
450
400
350
300
250
200
150
100
50
0
IFOUT
0
Figure 17. IFOUT 50 Ω Test Circuit
LPWR=0
500–600 MHz
600–800 MHz
Frequency
800–1 GHz
200
Table 8. L
Resistance at 550 MHz
L
MATCH
400
Load Resistance (Ω)
MATCH
LPWR=1
600
560 pF
Values
L
40 nH
27 nH
18 nH
800
MATCH
1000
50
Ω
1200
Rev. 1.4
Reference Frequency Amplifier
The Si4133G provides a reference frequency amplifier.
If the driving signal has CMOS levels it can be
connected directly to the XIN pin. Otherwise, the
reference frequency signal should be ac coupled to the
XIN pin through a 560 pF capacitor.
Powerdown Modes
Table 9 summarizes the powerdown functionality. The
Si4133G can be powered down by taking the PWDN pin
low or by setting bits in the Powerdown register
(Register 1). When the PWDN pin is low, the Si4133G
will be powered down regardless of the Powerdown
register settings. When the PWDN pin is high, power
management is controlled by the Powerdown register
bits.
The reference frequency amplifier, IF, and RF sections
of the Si4133G circuitry can be individually powered
down by setting the Powerdown register bits PDIB and
PDRB low, respectively. The reference frequency
amplifier is also powered up if the PDRB and PDIB bits
are high. Also, setting the AUTOPDB bit to 1 in the Main
Configuration register (Register 0) is equivalent to
setting both bits in the Powerdown register to 1. The
serial interface remains available and can be written in
all powerdown modes.
Auxiliary Output (AUXOUT)
The signal appearing on AUXOUT is selected by setting
the AUXSEL bits in the Main Configuration register
(Register 0).
The LDETB signal can be selected by setting the
AUXSEL bits to 11. This signal can indicate that the IF or
RF PLL is going to lose lock due to excessive ambient
temperature drift and should be re-tuned. The LDETB
signal indicates a logical OR result if both IF and RF are
simultaneously generating a signal.