LMX2377UTM National Semiconductor, LMX2377UTM Datasheet - Page 27

• Manufacturer Part Number: LMX2377UTM
• Description: IC FREQ SYNTH DUAL 20TSSOP
• Manufacturer: National Semiconductor
• Series: PLLatinum™r
• Type: PLL Frequency Synthesizerr

Specifications of LMX2377UTM

• Pll: Yes with Bypass
• Input: CMOS, TTL
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 3:1
• Differential - Input:output: Yes/No
• Frequency - Max: 2.5GHz, 1.2GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 2.5GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *LMX2377UTM

Test Setups
The block diagram above illustrates the setup required to
measure the LMX2377U device’s Main input sensitivity level.
The same setup is used for the LMX2370TMEB/
LMX2370SLEEB Evaluation Boards. The Aux input sensitiv-
ity test setup is similar to the Main input sensitivity test setup.
The purpose of this test is to measure the acceptable signal
level to the f
acceptable signal range, the feedback divider begins to di-
vide incorrectly and miscount the frequency.
The setup uses an open loop configuration. A power supply
is connected to V
to 5.5V. The MICROWIRE power supply, Vµc, is tied to V
The Aux PLL is powered down (PWDN Aux Bit = 1). By
means of a signal generator, an RF signal is applied to the
f
the PLL and the signal generator. The OSC
V
Main N_CNTRB Word = 312 and Main N_CNTRA Word =
16 for PRE Main Bit = 1. The feedback divider output is
routed to the F
IN
cc
Main pin. The 3 dB pad provides a 50 Ω match between
. The N value is typically set to 10000 in Code Loader, i.e.
IN
o
LD pin by selecting the Main PLL N Divider
Main input of the PLL chip. Outside the
cc
and the bias voltage is swept from 2.7V
(Continued)
LMX2377U f
in
pin is tied to
IN
cc
.
Sensitivity Test Setup
27
Output word (F
Universal Counter is connected to the F
the 10 MHz reference output of the signal generator. The
output of the feedback divider is thus monitored and should
be equal to f
The f
with the signal generator. The measurements are repeated
at different temperatures, namely T
+85˚C. Sensitivity is reached when the frequency error of the
divided RF input is greater than or equal to 1 Hz. The power
attenuation from the cable and the 3 dB pad must be ac-
counted for. The feedback divider will actually miscount if too
much or too little power is applied to the f
Therefore, the allowed input power level will be bounded by
the upper and lower sensitivity limits. In a typical application,
if the power level to the f
sensitivity limits, this can introduce spurs and degradation in
phase noise. When the power level gets even closer to these
limits, or exceeds it, then the Main PLL loses lock.
IN
Main input frequency and power level are then swept
IN
Main/ N.
o
LD Word = 6 or 14) in Code Loader. A
IN
Main input approaches the
A
= -40˚C, +25˚C, and
o
LD pin and tied to
IN
Main input.
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