MPC961CFA Freescale Semiconductor, MPC961CFA Datasheet - Page 9

• Manufacturer Part Number: MPC961CFA
• Description: IC ZDB CMOS LV 1:18 32-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Fanout Distribution, Zero Delay Bufferr

Specifications of MPC961CFA

• Pll: Yes
• Input: LVCMOS
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:17
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: No/No
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TIMING SOLUTIONS
DL207 — Rev 0
The time from the PLL controlled edge to the non controlled edge,
divided by the time between PLL controlled edges, expressed as a
percentage
The variation in cycle time of a signal between adjacent cycles, over a
random sample of adjacent cycle pairs
The pin–to–pin skew is defined as the worst case difference in prop-
agation delay between any similar delay path within a single device
t F
Figure 12. Output–to–output Skew t SK(O)
Figure 18. Output Transition Time Test
Figure 14. Output Duty Cycle (DC)
T N
Figure 16. Cycle–to–cycle Jitter
t P
T N+1
T 0
Reference
DC = t P /T 0 x 100%
t SK(O)
T JIT(CC) = |T N –T N+1 |
t R
Freescale Semiconductor, Inc.
V CC =3.3V
For More Information On This Product,
0.55
2.4
V CC =2.5V
V CC
V CC
GND
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1.8V
0.6V
V CC
V CC
GND
V OH
V CC
GND
B
B
B
2
2
2
9
CCLK
FB_IN
The deviation in cycle time of a signal with respect to the ideal period over
a random sample of cycles
The deviation in t 0 for a controlled edge with respect to a t 0 mean in a
random sample of cycles
CCLK
FB_IN
Figure 13. Propagation delay (t PD , static phase
T 0
t ( )
Figure 15. I/O Jitter
Figure 17. Period Jitter
offset) test reference
T JIT(PER) = |T N –1/f 0 |
T JIT
) = |T 0 –T 1 mean|
MPC961C
V CC
V CC
GND
V CC
V CC
GND
MOTOROLA
B
B
2
2