MC145157DW2 Freescale Semiconductor, MC145157DW2 Datasheet - Page 20

• Manufacturer Part Number: MC145157DW2
• Description: IC SER-IN PLL FREQ SYNTH 16-SOIC
• Manufacturer: Freescale Semiconductor
• Type: PLL Clock/Frequency Synthesizerr

Specifications of MC145157DW2

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: No/No
• Frequency - Max: 25MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 9 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Frequency-max: 25MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MC145151–2 through MC145158–2
20
NOTE: Sometimes R 1 is split into two series resistors, each R 1
DEFINITIONS:
RECOMMENDED READING:
Damping Factor:
Gardner, Floyd M., Phaselock Techniques (second edition). New York, Wiley–Interscience, 1979.
Manassewitsch, Vadim, Frequency Synthesizers: Theory and Design (second edition). New York, Wiley–Interscience, 1980.
Blanchard, Alain, Phase–Locked Loops: Application to Coherent Receiver Design. New York, Wiley–Interscience, 1976.
Egan, William F., Frequency Synthesis by Phase Lock. New York, Wiley–Interscience, 1981.
Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice–Hall, 1983.
Berlin, Howard M., Design of Phase–Locked Loop Circuits, with Experiments. Indianapolis, Howard W. Sams and Co., 1978.
Kinley, Harold, The PLL Synthesizer Cookbook. Blue Ridge Summit, PA, Tab Books, 1980.
AN535, Phase–Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970.
AR254, Phase–Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from Electronic Design,
for a typical design w n (Natural Frequency)
N = Total Division Ratio in feedback loop
K (Phase Detector Gain) = V DD /
K (Phase Detector Gain) = V DD /2 for V and R
K VCO (VCO Gain) =
1987.
filter V and R . The value of C C should be such that the corner frequency of this network does not significantly affect n .
The R and V outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the common mode input range of the
op amp used in the combiner/loop filter.
A)
C)
B)
PD out —
PD out
PD out
R
V
R —
V —
R —
V —
1
2
V VCO
f VCO
R 1
R 1
R 1
R 1
PHASE–LOCKED LOOP — LOW–PASS FILTER DESIGN
C
Freescale Semiconductor, Inc.
R 2
C
C
for PD out
For More Information On This Product,
R 2
R 2
_
+ A
VCO
VCO
2 fr
10
DESIGN CONSIDERATIONS
Go to: www.freescale.com
C
(at phase detector input).
VCO
2. A capacitor C C is then placed from the midpoint to ground to further
F(s) =
F(s) =
ASSUMING GAIN A IS VERY LARGE, THEN:
F(s) =
n =
n =
n =
=
=
=
0.5 n
(R 1 + R 2 )sC + 1
2K K VCO
R 2 sC + 1
R 1 sC + 1
R 1 sC
n R 2 C
N n
2
K K VCO
K K VCO
NC(R 1 + R 2 )
R 2 sC + 1
1
NCR 1
NR 1 C
K K VCO
R 2 C +
K K VCO
N
MOTOROLA