CY7B9910-7SC Cypress Semiconductor Corp, CY7B9910-7SC Datasheet
CY7B9910-7SC
Specifications of CY7B9910-7SC
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CY7B9910-7SC Summary of contents
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... Jitter: <200 ps peak to peak, <25 ps RMS • Compatible with Pentium™-based processors Functional Description The CY7B9910 and CY7B9920 Low Skew Clock Buffers offer low-skew system clock distribution. These multiple-output clock drivers optimize the timing of high-performance comput- er systems. Eight individual drivers can each drive terminated ...
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... Min Min 2.0 –0.5 Min. V Max. V – Min. V Max – 500 mV Min. V Max. 0 Max Max Max 0.4V –500 – CY7B9910 CY7B9920 Ambient Temperature + 10% – + 10% CY7B9920 Max. Min. Max. Unit V V –0.75 CC 0. – 1.35 0.8 –0.5 1. – – 500 mV 500 mV 500 mV 1 ...
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... Mil/Ind Selects Open Max., CCN CCQ OUT Input Selects Open, f MAX Max., CCN CCQ OUT Input Selects Open, f MAX Test Conditions MHz 5. CY7B9910 CY7B9920 CY7B9920 Max. Min. Max. Unit –200 –200 A –250 N [5] 78 104 mW Max. Unit Internal termination resistors hold unconnected ...
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... AC Test Loads and Waveforms 5V R1=130 R1 R2= (Includes fixture and probe capacitance 7B9910–3 TTL AC Test Load (CY7B9910 R1=100 R2=100 (Includes fixture and probe capacitance 7B9910–5 CMOS AC Test Load (CY7B9920) Switching Characteristics Over the Operating Range Parameter Description f Operating Clock NOM ...
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... JR Notes: 7. Test measurement levels for the CY7B9910 are TTL levels (1.5V to 1.5V). Test measurement levels for the CY7B9920 are CMOS levels (V conditions assume signal transition times of 2ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified. 8. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. ...
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... AC Timing Diagrams REF OTHER REF RPWL t RPWH t ODCV t ODCV t t SKEW SKEW 6 CY7B9910 CY7B9920 t JR 7B9910–8 ...
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... Q7 nated transmission lines (with impedances as low as 50 ohms), allows efficient printed circuit board design. Figure 2 shows the CY7B9910/9920 connected in series to construct a zero-skew clock distribution tree between boards. Cascaded clock buffers will accumulate low-frequency jitter because of the non-ideal filtering characteristics of the PLL filter ...
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... Ordering Code 250 CY7B9910–2SC CY7B9920–2SC 500 CY7B9910–5SC CY7B9910–5SI CY7B9920–5SC CY7B9920–5SI 750 CY7B9910–7SC CY7B9910–7SI CY7B9920–7SC CY7B9920–7SI Document #: 38–00437–B Package Diagram Package Name Package Type S13 24-Lead Small Outline IC S13 24-Lead Small Outline IC ...