NB7L32MMNG ON Semiconductor, NB7L32MMNG Datasheet

IC CLOCK DIVIDER 1:2 16-QFN

NB7L32MMNG

Manufacturer Part Number
NB7L32MMNG
Description
IC CLOCK DIVIDER 1:2 16-QFN
Manufacturer
ON Semiconductor
Type
Clock Dividerr
Datasheet

Specifications of NB7L32MMNG

Pll
No
Input
CML, ECL, LVDS, LVPECL
Output
CML
Number Of Circuits
1
Ratio - Input:output
1:1
Differential - Input:output
Yes/Yes
Frequency - Max
14GHz
Divider/multiplier
Yes/No
Voltage - Supply
2.375 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-TFQFN Exposed Pad
Frequency-max
14GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
NB7L32MMNG
Manufacturer:
ON/安森美
Quantity:
20 000
NB7L32M
2.5V/3.3V, 14GHz ÷2 Clock
Divider w/CML Output and
Internal Termination
Description
inputs and asynchronous reset.
resistors and accept LVPECL (Positive ECL), CML, or LVDS. The
high frequency reset pin is asserted on the rising edge. Upon
power−up, the internal flip−flops will attain a random state; the reset
allows for the synchronization of multiple NB7L32M’s in a system.
50 W termination which guarantees 400 mV output swing when
externally receiver terminated 50 W to V
Features
© Semiconductor Components Industries, LLC, 2010
July, 2010 − Rev. 2
The NB7L32M is an integrated ÷2 divider with differential clock
Differential clock inputs incorporate internal 50 W termination
The differential 16 mA CML output provides matching internal
The device is housed in a small 3x3 mm 16 pin QFN package.
Output Only
EP, and SG Devices
Maximum Input Clock Frequency 14 GHz Typical
200 ps Max Propagation Delay
30 ps Typical Rise and Fall Times
< 0.5 ps Maximum (RMS) Random Clock Jitter
Operating Range: V
CML Output Level (400 mV Peak−to−Peak Output), Differential
50 W Internal Input and Output Termination Resistors
Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
These are Pb−Free Devices
CC
= 2.375 V to 3.465 V with V
CC
(See Figure 15).
EE
= 0 V
1
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
Z = LOW to HIGH Transition
W = HIGH to LOW Transition
x = Don’t Care
VTCLK
VTCLK
CLK
*For additional marking information, refer to
CLK
CLK
CASE 485G
x
Z
MN SUFFIX
Application Note AND8002/D.
QFN−16
FUNCTIONAL BLOCK DIAGRAM
1
ORDERING INFORMATION
A
L
Y
W
G
50 W
50 W
CLK
http://onsemi.com
W
x
TRUTH TABLE
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Publication Order Number:
R
H
L
Divide by 2
1
Reset
DIAGRAM*
16
MARKING
R
÷2
Q
L
ALYWG
NB7L
R1
32M
NB7L32M/D
G
V
CC
V
÷2
H
Q
EE
Q
Q

Related parts for NB7L32MMNG

NB7L32MMNG Summary of contents

Page 1

NB7L32M 2.5V/3.3V, 14GHz ÷2 Clock Divider w/CML Output and Internal Termination Description The NB7L32M is an integrated ÷2 divider with differential clock inputs and asynchronous reset. Differential clock inputs incorporate internal 50 W termination resistors and accept LVPECL (Positive ECL), ...

Page 2

VTCLK VTCLK Table 1. PIN DESCRIPTION Pin Name I/O 1 VTCLK − 2 CLK ECL, CML, LVDS Input 3 CLK ECL, CML, LVDS Input 4 VTCLK − − − 12, 13, V ...

Page 3

Table 2. ATTRIBUTES Internal Input Pulldown Resistor ESD Protection Moisture Sensitivity (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS Symbol Parameter ...

Page 4

Table 4. DC CHARACTERISTICS, CLOCK INPUTS, CML OUTPUTS T = −40°C to +85°C A Symbol I Power Supply Current (Note Output HIGH Voltage (Note Output LOW Voltage (Note Internal Output Termination ...

Page 5

Table 6. AC CHARACTERISTICS V Symbol Characteristic V Output Voltage Amplitude (@ V OUTPP (See Figures and 6) f Maximum Input Clock Frequency IN (See Figure Propagation Delay to PLH t Output Differential ...

Page 6

TIME (190 ps/div) Figure 3. Typical Output Waveform with GHz 2 400 mV INPP Room Temperature 357 mV, OUTPP ps ps, f ...

Page 7

Q Driver Device Q Figure 8. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8073/D − Termination of CML Logic Devices.) CLK V th CLK V th Figure 9. Differential Input Driven Single−Ended ...

Page 8

All NB7L32M inputs can accept PECL, CML, and LVDS signal levels. The limitations for differential input signal (LVDS, PECL, or CML) are minimum input swing of 150 mV and the maximum input swing of 2500 mV. Within these conditions, the ...

Page 9

... V CC LVDS Driver V EE ORDERING INFORMATION Device NB7L32MMNG NB7L32MMNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. APPLICATION INFORMATION VTD VTD Figure 16. LVDS to NB7L32M Interface Package QFN−16 (Pb− ...

Page 10

... 0.05 C NOTE 3 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 6,362,644. N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81− ...

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