ICS952601EFLF IDT, Integrated Device Technology Inc, ICS952601EFLF Datasheet

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Programmable Timing Control Hub TM Gen P4 Processor Recommended Application: CK409 clock, Intel Yellow Cover part Output Features: • 0.7V current-mode differential CPU pairs • 0.7V current-mode differential SRC pair • PCI (33MHz) • ...

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ICS952601 Programmable Timing Control Hub Pin Description PIN PIN NAME PIN TYPE # 1 REF0 OUT 2 REF1 OUT 3 VDDREF PWR OUT 6 GND PWR 7 PCICLK_F0 OUT 8 PCICLK_F1 OUT 9 PCICLK_F2 OUT ...

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ICS952601 Programmable Timing Control Hub Pin Description (continued) PIN PIN NAME PIN TYPE # 29 3V66_4/VCH OUT 30 SDATA I/O 31 48MHz_USB OUT 32 48MHz_DOT OUT 33 GND PWR 34 VDD48 PWR 35 Vtt_PWRGD VDD PWR 37 SRCCLKC ...

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ICS952601 Programmable Timing Control Hub General Description ICS952601 follows Intel CK409 Yellow Cover specification. This clock synthesizer provides a single chip solution for next generation P4 Intel processors and Intel chipsets. ICS952601 is driven with a 14.318MHz crystal. It generates ...

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ICS952601 Programmable Timing Control Hub Absolute Maximum Ratings Symbol Parameter VDD_A 3.3V Core Supply Voltage VDD_In 3.3V Logic Input Supply Voltage Ts Storage Temperature Tambient Ambient Operating Temp Tcase1 Case Temperature 1 Tcase2 Case Temperature 2 ESD prot Input ESD ...

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ICS952601 Programmable Timing Control Hub Electrical Characteristics - CPU & SRC 0.7V Current Mode Differential Pair 70° 3.3 V +/-5 PARAMETER SYMBOL Current Source Output Zo Impedance Voltage High VHigh Voltage ...

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ICS952601 Programmable Timing Control Hub Electrical Characteristics - 3V66 Mode: 3V66 [4: 70° 3.3 V +/-5 PARAMETER SYMBOL Long Accuracy ppm T Clock period period V Output High Voltage Output ...

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ICS952601 Programmable Timing Control Hub Electrical Characteristics - 48MHz DOT Clock 70° 3.3 V +/-5 PARAMETER SYMBOL Long Accuracy ppm T Clock period period V Output High Voltage OH V Output ...

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ICS952601 Programmable Timing Control Hub Electrical Characteristics - REF-14.318MHz 70° 3.3 V +/-5 PARAMETER SYMBOL Long Accuracy Clock period Output High Voltage Output Low Voltage Output High Current Output Low Current ...

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ICS952601 Programmable Timing Control Hub 2 General I C serial interface information for the ICS952601 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller ...

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ICS952601 Programmable Timing Control Hub Table: Read-Back Register Byte 0 Pin # - RESERVED Bit 7 Bit 6 - RESERVED - RESERVED Bit 5 Bit 4 - RESERVED PCI_STOP# Bit 3 - Bit 2 - CPU_STOP# Bit ...

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ICS952601 Programmable Timing Control Hub Table: Output Control Register Byte 3 Pin # 7,8,9,12,13,14,15, Bit 7 18,19,20,37,38, Bit 6 20 Bit 5 19 Bit Bit 3 14 Bit 2 13 Bit 1 12 Bit ...

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ICS952601 Programmable Timing Control Hub Table: Output Control and Fix Frequency Register Byte 6 Pin # 1,2,7,8,9,12,13,14,1 5,18,19,20,22,23,26, Bit 7 Test Clock Mode 27,29,31,32,37,38,4 0,41,43,44,46,47 Bit 6 - RESERVED 40,41,43,44,46,47 Bit 5 RESERVED 37,38 Bit 4 RESERVED ...

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ICS952601 Programmable Timing Control Hub PCI Stop Functionality The PCI_STOP# signal active low input controlling PCI and SRC outputs. If PCIF (2:0) and SRC clocks can be set to be free-running through I2C programming. Outputs set to ...

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ICS952601 Programmable Timing Control Hub CPU_STOP# Functionality The CPU_STOP# signal is an active low input controlling the CPU outputs. This signal can be asserted asynchronously ...

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ICS952601 Programmable Timing Control Hub PD#, Power Down PD asynchronous active low input used to shut off all clocks cleanly prior to clock power. When PD# is asserted low all clocks will be driven low before turning off ...

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ICS952601 Programmable Timing Control Hub PD# De-assertion The time from the de-assertion of PD# or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive mode control bit for PD# tristate is programmed to ...

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ICS952601 Programmable Timing Control Hub Differential Clock Tristate To minimize power consumption, CPU[2:0] clock outputs are individually configurable through SMBus to be driven or tristated during PwrDwn# and CPU_Stop# mode and the SRC clock is configurable to be driven or ...

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ICS952601 Programmable Timing Control Hub CPU Clock Tristate Timing The following diagrams illustrate CPU clock timing during CPU_Stop# and PwrDwn# modes with CPU_PwrDwn and CPU_Stop tristate control bits set to driven or tristate in byte 2 of the control register. ...

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ICS952601 Programmable Timing Control Hub CPU_Stop# PWRDWN# CPU (Free Running) CPU# (Free Running) CPU (Stoppable) CPU# (Stoppable) Notes: 1. When CPU_Pwrdwn is set to tristate and CPU_Stop is set to driven, the clock chip will tristate outputs only during the ...

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ICS952601 Programmable Timing Control Hub SRC Clock Tristate Timing The following diagrams illustrate SRC clock timing during PCI_Stop# and PwrDwn# modes with SRC_Pwrdwn and SRC_Stop tristate control bits set to driven or tristate in byte 2 of the control register. ...

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ICS952601 Programmable Timing Control Hub PCI_Stop# PCI (Free Running) PWRDWN# CPU (Free Running) CPU# (Free Running) SRC (Stoppable) SRC# (Stoppable) Notes: 1. When SRC_Pwrdwn and SRC_Stop are set to tristate, the clock chip will tristate outputs during the assertion of ...

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ICS952601 Programmable Timing Control Hub INDEX INDEX AREA AREA 45° .10 (.004) C .10 (.004) C Ordering Information 952601yFLFT Example: XXXX Progammable Timing Control ...

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ICS952601 Programmable Timing Control Hub INDEX INDEX AREA AREA Ordering Information 952601yGLFT Example: XXXX Progammable Timing Control Hub TM TM IDT TM for ...

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ICS952601 Programmable Timing Control Hub Revision History Rev. Issue D ate Description I 5/4/2005 Updated Ordering Information from "Lead Free" to "Annealed Lead Free" J 1/25/2010 Update document template TM TM for Next Gen P4 TM Processor Innovate with IDT ...