IDT2305A-1DCI IDT, Integrated Device Technology Inc, IDT2305A-1DCI Datasheet - Page 5

• Manufacturer Part Number: IDT2305A-1DCI
• Description: IC CLK BUFFER ZD 3.3V 8-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Zero Delay Bufferr

Specifications of IDT2305A-1DCI

• Pll: Yes with Bypass
• Input: LVTTL
• Output: LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 1:5
• Differential - Input:output: No/No
• Frequency - Max: 133MHz
• Divider/multiplier: No/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC
• Frequency-max: 133MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 2305A-1DCI

SWITCHING CHARACTERISTICS (2305A-1) - INDUSTRIAL
NOTES:
1. REF Input has a threshold voltage of V
2. All parameters specified with loaded outputs.
SWITCHING CHARACTERISTICS (2305A-1H) - INDUSTRIAL
NOTES:
1. REF Input has a threshold voltage of V
2. All parameters specified with loaded outputs.
ZERO DELAY AND SKEW CONTROL
loading can affect and adjust the input/output delay.
load equal to that on the other outputs in order to obtain true zero I/O Delay. If I/O Delay adjustments are needed, use the Output Load Difference diagram
to calculate loading differences between the CLKOUT pin and other outputs. For zero output-to-output skew, all outputs must be loaded equally.
IDT2305A
3.3V ZERO DELAY CLOCK BUFFER
Symbol
Symbol
For designs utilizing zero I/O Delay, all outputs including CLKOUT must be equally loaded. Even if the output is not used, it must have a capacitive
t
t
All outputs should be uniformly loaded in order to achieve Zero I/O Delay. Since the CLKOUT pin is the internal feedback for the PLL, its relative
LOCK
LOCK
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
3
4
5
6
7
J
1
3
4
5
6
7
8
J
Output Frequency
Duty Cycle = t
Rise Time
Fall Time
Output to Output Skew
Delay, REF Rising Edge to CLKOUT Rising Edge
Device-to-Device Skew
Cycle-to-Cycle Jitter, pk - pk
PLL Lock Time
Output Frequency
Duty Cycle = t
Duty Cycle = t
Rise Time
Fall Time
Output to Output Skew
Delay, REF Rising Edge to CLKOUT Rising Edge
Device-to-Device Skew
Output Slew Rate
Cycle-to-Cycle Jitter, pk - pk
PLL Lock Time
2
2
2
÷ t
÷ t
÷ t
Parameter
Parameter
1
1
1
DD
DD
/2.
/2.
Measured at V
Measured at V
10pF Load
30pF Load
Measured at 1.4V, F
Measured between 0.8V and 2V
Measured between 0.8V and 2V
All outputs equally loaded
Measured at V
Measured at 66.66MHz, loaded outputs
Stable power supply, valid clock presented on REF pin
10pF Load
30pF Load
Measured at 1.4V, F
Measured at 1.4V, F
Measured between 0.8V and 2V
Measured between 0.8V and 2V
All outputs equally loaded
Measured at V
Measured between 0.8V and 2V using Test Circuit #2
Measured at 66.66MHz, loaded outputs
Stable power supply, valid clock presented on REF pin
5
DD
DD
DD
DD
/2
/2
/2 on the CLKOUT pins of devices
/2 on the CLKOUT pins of devices
Conditions
Conditions
OUT
OUT
OUT
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
= 66.66MHz
= 66.66MHz
<50MHz
(1,2)
(1,2)
Min.
Min.
10
10
40
—
—
—
—
—
—
—
10
10
40
45
—
—
—
—
—
—
—
1
Typ.
Typ.
—
—
50
—
—
—
—
—
—
—
50
50
—
—
—
—
—
—
0
0
0
0
±350
±350
Max.
Max.
133
100
250
700
200
133
100
250
700
200
2.5
2.5
1.5
1.5
60
60
55
—
1
1
MHz
MHz
Unit
Unit
V/ns
ms
ms
%
%
%
ns
ns
ps
ps
ps
ps
ns
ns
ps
ps
ps
ps