CY23S05SXC-1H Cypress Semiconductor Corp, CY23S05SXC-1H Datasheet - Page 2

• Manufacturer Part Number: CY23S05SXC-1H
• Description: IC CLK ZDB 5OUT 133MHZ 8SOIC
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Distribution, Zero Delay Bufferr
• Series: Spread Aware™r

Specifications of CY23S05SXC-1H

• Number Of Circuits: 1
• Package / Case: 8-SOIC (3.9mm Width)
• Pll: Yes
• Input: LVCMOS, LVTTL
• Output: LVCMOS
• Ratio - Input:output: 1:5
• Differential - Input:output: No/No
• Frequency - Max: 133.33MHz
• Divider/multiplier: No/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Frequency-max: 133MHz
• Output Frequency Range: 10 MHz to 133.33 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2215-5; CY23S05SXC-1H

Select Input Decoding for CY23S09
Zero Delay and Skew Control
All outputs must be uniformly loaded to achieve Zero Delay
between the input and output. Because the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the
input-output delay. This is shown in the above graph.
For applications requiring zero input-output delay, all outputs,
including CLKOUT, must be equally loaded. Even if CLKOUT is
not used, it must have a capacitive load equal to that on other
outputs, to obtain zero input-output delay. If input to output delay
adjustments are required, use the above graph to calculate
loading differences between the CLKOUT pin and other outputs.
For zero output-output skew, be sure to load all outputs equally.
For further information, refer to the application note “CY23S05
and CY23S09 as PCI and SDRAM Buffers.”
Pinouts
Figure 1. Pin Configuration – CY23S09
Document Number: 38-07296 Rev. *F
Note
1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
S2
0
0
1
1
S1
0
1
0
1
CLOCK A1–A4
Three-state
Driven
Driven
Driven
CLOCK B1–B4
Three-state
Three-state
Driven
Driven
CLKOUT
Spread Aware
Many systems being designed now use a technology called
Spread Spectrum Frequency Timing Generation. Cypress is one
of the pioneers of SSFTG development and designed this
product so as not to filter off the Spread Spectrum feature of the
Reference input, assuming it exists. When a zero delay buffer is
not designed to pass the SS feature through, the result is a signif-
icant amount of tracking skew, which may cause problems in
systems requiring synchronization.
For more details on Spread Spectrum timing technology, please
see the Cypress application note AN1278, EMI Suppression
Techniques with Spread Spectrum Frequency Timing Generator
(SSFTG) ICs.
Figure 2. Pin Configuration – CY23S05
Driven
Driven
Driven
Driven
[1]
Output Source
Reference
PLL
PLL
PLL
CY23S09, CY23S05
PLL Shutdown
N
N
Y
N
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