CY7B991-5JC Cypress Semiconductor Corp, CY7B991-5JC Datasheet - Page 12

• Manufacturer Part Number: CY7B991-5JC
• Description: IC CLK BUFF SKEW 8OUT 32PLCC
• Manufacturer: Cypress Semiconductor Corp
• Type: Buffer/Driverr
• Series: RoboClock™r

Specifications of CY7B991-5JC

• Number Of Circuits: 1
• Package / Case: 32-PLCC
• Ratio - Input:output: 8:8
• Differential - Input:output: Yes/Yes
• Input: 3-State, TTL
• Output: TTL
• Frequency - Max: 80MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Frequency-max: 80MHz
• Output Frequency Range: 3.75 MHz to 80 MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 5 V
• Number Of Elements: 1
• Supply Current: 85mA
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: PLCC
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Pin Count: 32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1375

Figure 8 shows the CY7B991/992 connected in series to con-
struct a zero-skew clock distribution tree between boards. De-
lays of the downstream clock buffers can be programmed to
compensate for the wire length (i.e., select negative skew
equal to the wire delay) necessary to connect them to the mas-
Document #: 38-07138 Rev. **
DISTRIBUTION
SYSTEM
CLOCK
20–MHz
CLOCK
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
Figure 8. Board-to-Board Clock Distribution
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
Figure 7. Multi-Function Clock Driver
REF
REF
ter clock source, approximating a zero-delay clock tree. Cas-
caded clock buffers will accumulate low-frequency jitter be-
cause of the non-ideal filtering characteristics of the PLL filter.
It is recommended that not more than two clock buffers be
connected in series.
SKEWED –3.125 ns (–4t
80-MHz
L4
L1
ZERO SKEW
L2
L3
INVERTED
80-MHz
20-MHz
80-MHz
Z
0
U
)
Z
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
0
Z
Z
0
Z
0
0
Z
Z
Z
0
0
0
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
7B991–14
CY7B991
CY7B992
Page 12 of 15
LOAD
7B991–15
LOAD