MC10E195FN ON Semiconductor, MC10E195FN Datasheet - Page 7

• Manufacturer Part Number: MC10E195FN
• Description: IC PROGRAM DELAY ECL 5V 28PLCC
• Manufacturer: ON Semiconductor
• Series: 10Er
• Type: Programmable Delay Chipr

Specifications of MC10E195FN

• Input: ECL
• Output: ECL
• Frequency - Max: 1GHz
• Voltage - Supply: 4.2 V ~ 5.7 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Frequency-max: 1GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: MC10E195FNOS

Cascading Multiple E195’s
cascade circuitry has been included. This circuitry allows for
the cascading of multiple E195’s without the need for any
external gating. Furthermore this capability requires only
one more address line per added E195. Obviously cascading
multiple PDC’s will result in a larger programmable range
however this increase is at the expense of a longer minimum
delay.
two E195’s. As can be seen, this scheme can easily be
expanded for larger E195 chains. The D7 input of the E195
is the cascade control pin. With the interconnect scheme of
Figure 3 when D7 is asserted it signals the need for a larger
programmable range than is achievable with a single device.
pictured below. Use of this diagram will simplify the
explanation of how the cascade circuitry works. When D7
of chip #1 above is low the cascade output will also be low
while the cascade bar output will be a logical high. In this
condition the SET MIN pin of chip #2 will be asserted and
thus all of the latches of chip #2 will be reset and the device
will be set at its minimum delay. Since the RESET and SET
inputs of the latches are overriding any changes on the
A0−A6 address bus will not affect the operation of chip #2.
SET MAX
SET MIN
To increase the programmable range of the E195 internal
Figure 3 illustrates the interconnect scheme for cascading
An expansion of the latch section of the block diagram is
LEN
Reset Reset
D0
BIT 0
Q0
INPUT
A7
LEN
D1
Reset Reset
BIT 1
Figure 4. Expansion of the Latch Section of the E195 Block Diagram
Q1
D1
D0
LEN
V
IN
IN
V
EE
BB
Reset Reset
D2
LEN
BIT 2
Figure 3. Cascading Interconnect Architecture
Q2
TO SELECT MULTIPLEXERS
Chip #1
E195
Reset Reset
D3
LEN
BIT 3
ADDRESS BUS (A0−A6)
http://onsemi.com
Q3
V
V
V
CCO
CCO
CC
Q
Q
7
Reset Reset
D4
LEN
BIT 4
SET MAX de-asserted so that its delay will be controlled
entirely by the address bus A0−A6. If the delay needed is
greater than can be achieved with 31.75 gate delays
(1111111 on the A0−A6 address bus) D7 will be asserted to
signal the need to cascade the delay to the next E195 device.
When D7 is asserted the SET MIN pin of chip #2 will be
de-asserted and the delay will be controlled by the A0−A6
address bus. Chip #1 on the other hand will have its SET
MAX pin asserted resulting in the device delay to be
independent of the A0−A6 address bus.
D1 latches will be reset while the rest of the latches will be
set. In addition, to maintain monotonicity an additional gate
delay is selected in the cascade circuitry. As a result when D7
of chip #1 is asserted the delay increases from 31.75 gates
to 32 gates. A 32 gate delay is the maximum delay setting for
the E195.
simply needs to connect the D7 input and CASCADE
outputs of the current most significant E195 to the new most
significant E195 in the same manner as pictured in Figure 3.
The only addition to the logic is the increase of one line to
the address bus for cascade control of the second PDC.
Chip #1 on the other hand will have both SET MIN and
When the SET MAX pin of chip #1 is asserted the D0 and
To expand this cascading scheme to more devices one
Q4
D1
D0
LEN
V
IN
IN
V
EE
BB
Reset Reset
D5
LEN
BIT 5
Q5
Chip #2
E195
Reset Reset
LEN
D6
BIT 6
Q6
V
V
V
CCO
CCO
CC
Q
Q
Reset Reset
D7
LEN
BIT 7
OUTPUT
Q7
CASCADE
CASCADE