SI5365-C-GQ Silicon Laboratories Inc, SI5365-C-GQ Datasheet - Page 6

• Manufacturer Part Number: SI5365-C-GQ
• Description: IC CLOCK MULTIPLIER PROG 100TQFP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5365-C-GQ

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5365
1. Functional Description
The Si5365 is a low jitter, precision clock multiplier for
high-speed communication systems, including SONET
OC-48/OC-192, SDH STM-16/STM-64, Ethernet, and
Fibre Channel, in which the application requires clock
multiplication without jitter attenuation. The Si5365
accepts four clock inputs ranging from 19.44 to
707 MHz and generates five frequency-multiplied clock
outputs ranging from 19.44 to 1050 MHz. By default the
four clock inputs are at the same frequency and the five
clock outputs are at the same frequency. Two of the
output clocks can be divided down further to generate
an integer sub-multiple frequency. The input clock
frequency and clock multiplication ratio are selectable
from a table of popular SONET, Ethernet, and Fibre
Channel
multiplication in SONET and datacom applications, the
Si5365
translations. Silicon Laboratories offers a PC-based
software utility, DSPLLsim, that can be used to look up
valid Si5365 frequency translations. This utility can be
downloaded from
Documentation).
The Si5365 is based on Silicon Laboratories' 3rd-
generation DSPLL
rate frequency synthesis in a highly integrated PLL
solution that eliminates the need for external VCXO and
loop filter components. The Si5365 PLL loop bandwidth
is digitally programmable via the BWSEL[1:0] pins and
supports a range from 30 kHz to 1.3 MHz. The
DSPLLsim software utility can be used to calculate valid
loop bandwidth settings for a given input clock
frequency/clock multiplication ratio.
The Si5365 monitors all input clocks for loss-of-signal
and provides a LOS alarm when it detects a missing
clock.
In the case when the input clocks enter alarm
conditions, the PLL will freeze the DCO output
frequency near its last value to maintain operation with
an internal state close to the last valid operating state.
The Si5365 has five differential clock outputs. The
signal format of the clock outputs is programmable to
support LVPECL, LVDS, CML, or CMOS loads. If not
required, unused clock outputs can be powered down to
minimize
debugging, a bypass mode is available which drives the
output clock directly from the input clock, bypassing the
internal DSPLL. The device is powered by a single 1.8
or 2.5 V supply.
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1.1. Further Documentation
Consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual (FRM) for detailed
information about the Si5365. Additional design support
is available from Silicon Laboratories through your
distributor.
Silicon Laboratories has developed a PC-based
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. The FRM and this utility can be
downloaded from http://www.silabs.com/timing; click on
Documentation.