IDTCV136PAG IDT, Integrated Device Technology Inc, IDTCV136PAG Datasheet - Page 11

• Manufacturer Part Number: IDTCV136PAG
• Description: IC FLEXPC CLK ATI RS400 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: FlexPC™r
• Type: PC Clockr

Specifications of IDTCV136PAG

• Input: Crystal
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: CV136PAG

ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT
PARAMETERS
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
NOTES:
1. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
2. This parameter is guaranteed by design, but not 100% production tested.
3. See TIMING DIAGRAMS for timing requirements.
IDTCV136
PROGRAMMABLE FLEXPC™ CLOCK FOR ATI RS400
Symbol
I
I
V
V
DD3.3OP
DD3.3PD
T
C
C
IH
IL
L
C
V
V
I
I
STAB
I
IL1
IL2
F
OUT
PIN
_FS
IH
INX
_FS
IH
IL
IN
I
Input HIGH Voltage
Input LOW Voltage
3.3V Input HIGH Voltage
3.3V Input LOW Voltage
Input HIGH Current
Input LOW Current
Input LOW Current
Operating Supply Current
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance
Modulation Frequency
T
Clock Stabilization
T
T
T
T
T
T
RISE
FALL
SU
SU
SU
DRIVE
DRIVE
_PD#
_SRC
_CPU
_PD#
_PD#
_SRC
_CPU_Stop#
A
(2)
(2)
= 0°C to +70°C, Supply Voltage: V
(2)
(2)
Parameter
(2)
(2)
(1)
(2)
(2,3)
(2)
(2)
3.3V ± 5%
3.3V ± 5%
V
V
V
V
Full active, C
All differential pairs driven
All differential pairs tri-stated
V
Logic inputs
Output pin capacitance
X1 and X2 pins
Triangular modulation
Stop response of all clocks after PD# assertion
From V
Rise time of PD#
Fall time of PD#
CPU output disable after CPU_Stop# assertion
CPU output enable after CPU_Stop# de-assertion
SRC output disable after CLKREQ# assertion
SRC output enable after CLKREQ# de-assertion
DD
IN
IN
IN
DD
= V
= 0V, inputs with no pull-up resistors
= 0V, inputs with pull-up resistors
= 3.3V
DD
DD
DD
power-up or de-assertion of PD# to first clock
= 3.3V ± 5%
L
= full load
Test Conditions
11
COMMERCIAL TEMPERATURE RANGE
V
V
SS
SS
Min.
–200
0.7
–5
–5
—
—
—
—
—
—
—
—
30
—
—
—
—
—
—
—
—
2
- 0.3
- 0.3
14.31818
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
V
V
DD
DD
Max.
0.35
400
100
0.8
1.8
—
—
70
12
—
33
60
60
60
60
5
7
5
6
5
5
5
+ 0.3
+ 0.3
MHz
Unit
KHz
µ A
µ A
µ A
mA
mA
nH
ms
pF
ns
ns
ns
ns
ns
ns
ns
V
V
V
V