IDTCV132BPVG8 IDT, Integrated Device Technology Inc, IDTCV132BPVG8 Datasheet - Page 4

• Manufacturer Part Number: IDTCV132BPVG8
• Description: IC FLEXPC CLK PROGR P4 56-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: FlexPC™r
• Type: PC Clockr

Specifications of IDTCV132BPVG8

• Input: Crystal
• Output: Clock
• Frequency - Max: 200MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: CV132BPVG8

PIN DESCRIPTION (CONT.)
SM BUS PROTOCOL
INDEX BLOCK WRITE PROTOCOL
IDTCV132B
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
Pin Number
11-18
20-27
29-36
38-45
Bit
2-9
10
19
28
37
46
1
45
46
47
48
49
50
51
52
53
54
55
56
# of bits
1
8
1
8
1
8
1
8
1
8
1
Master
Master
Master
Master
Master
Master
From
Slave
Slave
Slave
Slave
Slave
V
V
V
CPU2#
DD
SS
SS
CPU2
Name
IREF
V
FSA
V
FSB
_CPU
_IREF
_CPU
NC
NC
DDA
SSA
Start
D2h
Acknowledge
Acknowledge
Byte count N (0 is not a valid byte count)
Acknowledge
First data byte
Acknowledge
Second data byte
Acknowledge
:
Nth data byte
Stop
Register offset byte (starting byte)
Type
GND
PWR
GND
GND
PWR
OUT
OUT
OUT
Description
I N
I N
GND
Host 0.7V current mode differential clock output
Host 0.7V current mode differential clock output
3.3V
No Connection
No Connection
CPU frequency select, latched at V
Differential reference current
Host 0.7V current mode differential clock output
Analog V
Analog V
GND
SS
DD
4
INDEX BLOCK READ PROTOCOL
11-18
21-28
30-37
39-46
48-55
Bit
2-9
10
19
20
29
38
47
1
# of bits
TT
1
8
1
8
1
1
8
1
8
1
8
1
8
_P
WRGD
Master
Master
Master
Master
Master
Master
Slave
Master
Master
From
Slave
Slave
Slave
Slave
Slave
Slave
Slave
# assertion
Description
COMMERCIAL TEMPERATURE RANGE
Start
D2h
Acknowledge
Acknowledge
Repeated start
D3h
Acknowledge
Byte count, N, SMBus table byte 8 value.
Power on default is 0FH[15].
Acknowledge
Offset data byte, specified by bit 11-18
Acknowledge
Offset + 1 data byte
:
Offset + N-2
Acknowledge
Offset + N-1
Not acknowledge
Stop
Register offset byte (starting byte)
Description