IDTCV142PAG8 IDT, Integrated Device Technology Inc, IDTCV142PAG8 Datasheet - Page 4

• Manufacturer Part Number: IDTCV142PAG8
• Description: IC FLEXPC CLK PROGR P4 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: FlexPC™r
• Type: PC Clockr

Specifications of IDTCV142PAG8

• Input: Crystal
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: CV142PAG8

PIN DESCRIPTION (CONT.)
INDEX BLOCK WRITE PROTOCOL
INDEX BYTE WRITE
Setting bit[11:18] = starting address, bit[20:27] = 01h.
IDTCV142
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
Pin Number
11-18
20-27
29-36
38-45
Bit
2-9
10
19
28
37
46
1
43
44
45
46
47
48
49
50
51
52
53
54
55
56
# of bits
1
8
1
8
1
8
1
8
1
8
1
FSC/TEST_SEL
CPU_STOP#
PCI_STOP#
Master
Master
Master
Master
Master
Master
Master
XTAL_OUT
Master
From
Slave
Slave
Slave
Slave
Slave
V
V
Slave
V
XTAL_IN
CPU0#
SS
DD
CPU0
SS
Name
PCI0
SDA
SCL
REF
_CPU
_REF
_REF
Start
D2h
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Byte count, N (0 is not valid)
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
:
Nth data byte
Acknowledge
Stop
Type
GND
PWR
GND
OUT
OUT
OUT
OUT
OUT
I/O
IN
I N
I N
IN
IN
Description
Host 0.7 current mode differential clock output
Host 0.7 current mode differential clock output
GND
SM bus clock
SM bus data
3.3V
XTAL output
XTAL input
GND
14.318 MHz reference clock output
CPU frequency selection. Selects test mode if pulled above 2V when V
Stop all stoppable CPU CLK
Stop all stoppable PCI, SRC CLK
PCI clock
4
INDEX BYTE READ
Setting bit[11:18] = starting address. After reading back the first data byte,
master issues Stop bit.
INDEX BLOCK READ PROTOCOL
Master can stop reading any time by issuing the stop bit without waiting
until Nth byte (byte count bit30-37).
11-18
21-28
30-37
39-46
48-55
Bit
2-9
10
19
20
29
38
47
1
# of bits
1
8
1
8
1
1
8
1
8
1
8
1
8
Master
Master
Master
Master
Master
Master
Master
Master
Master
From
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Description
COMMERCIAL TEMPERATURE RANGE
Start
D2h
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Repeated Start
D3h
Ack (Acknowledge)
Byte count, N (block read back of N
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
Ack (Acknowledge)
Nth data byte
Not acknowledge
Stop
bytes), power on is 8
:
TT
Description
_P
WRGD
# is asserted LOW.