ICS9EPRS525AGILF IDT, Integrated Device Technology Inc, ICS9EPRS525AGILF Datasheet - Page 11

• Manufacturer Part Number: ICS9EPRS525AGILF
• Description: IC EMBEDDED PC MAIN CLK 56TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS9EPRS525AGILF

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1946

IDT
Table 7. PLL Modes for PCI3 Configurations
*Note: In Mode 3, Byte 8, bit (1:0) must be set to '1' to enable pin 17,18
Table 3: IO_Vout select table
Table 4: Device ID table
Table 5: Slew Rate Selection Table
Table 6. PCI3 Configuration Table
Table 8. ME Clock Selection Table
PCI3/CFG0
0 = Default
B9b2
B8b7
Bit 1
ICS9EPRS525
56-pin CK505 for Embedded Systems
HW Strap
TM
ITP_EN
Config
PCIF5/
0
0
0
0
1
1
1
1
0
0
0
1
1
Mode
High
High
Low
Mid
56-pin CK505 for Embedded Intel Systems
1
2
3
x
x
1
1
B9b1
B8b6
Bit 0
0
0
1
1
0
0
1
1
0
0
1
0
1
CPU/SRC/
PCI2/TME
iAMT_EN
Outputs
HW Strap
TME=0
TME=1
CPU
CPU
CPU
0 or 1
0 or 1
PCI
B8b5
1
1
1
1
B9b0
0.8X (1.6 V/ns)
0.7X (1.4V/ns)
0
1X (2.0 V/ns)
0
1
0
1
0
1
0
1
Slew Rate
PLL1
HI-Z
CPU2_AMT_EN CPU1_AMT_EN
(Byte 11, bit 7)
IO_Vout
B8b4
Note: 2 bits are needed since
PCI3_CFG1
0.3V
0.4V
0.5V
0.6V
0.7V
0.8V
0.9V
1.0V
0
Center
Center
Down
Down
SSC
CFG0 is tri-level input
0
0
1
1
0
0
1
1
56 pin TSSOP
Comment
USB/LAN25
(Byte 11, bit 6)
Outputs
PCI3_CFG0
USB
USB
USB
0
1
0
1
0
1
0
1
PLL2
11
Default, CPU1 = iAMT Clock
CPU2 = iAMT Clock
CPU1 and CPU2 both run in iAMT mode
SRC_Main_SE
(Byte 0, bit 2)
SSC
NA
NA
NA
NA
L
0
1
1
1
Description
SRC/PCI
SRC/PCI
SRC/PCI
Outputs
Reserved
Config Mode
0 = Default
-
PLL3
1
2
3
Down
Down
Down
SSC
-
25MHz SE
100MHz
100MHz
100MHz
SRC1
1614B—01/21/10
PLL Source
(Table 2
applies)
PLL2*
PLL1
PLL3
PLL3