ICS9LPRS436CKLF IDT, Integrated Device Technology Inc, ICS9LPRS436CKLF Datasheet - Page 13

• Manufacturer Part Number: ICS9LPRS436CKLF
• Description: IC CLK SYNTHESIZER 48VQFN
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS9LPRS436CKLF

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1935

IDT
SMBus Table: Frequency Select Register
SMBus Table: Output Control Register
SMBus Table: Output Control Register
SMBus Table: Output Control Register
NOTE: Only 1 PEREQ at a time can be selected to control an output.
Byte 0
Byte 1
Byte 2
Byte 3
ICS9LPRS436C
Low Power Clock for Intel Atom
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
®
Low Power Clock for Intel Atom
PEREQ3# Control
PEREQ3# Control
PEREQ2# Control
PEREQ2# Control
PEREQ1# Control
PEREQ1# Control
CPU PLL MN_EN
Spread Enable
USB_48MHz
SATA/PCIe3
PCICLK_F0
12.288MHz
DOT96Mhz
12_48MHz
ITP/PCIe2
CPUCLK1
CPUCLK0
Reserved
Reserved
PCICLK0
25MHz
25MHz
Name
Name
Name
Name
PCIe1
PCIe0
FSLC
FSLB
FSLA
REF0
FS4
FS3
®
-Based Systems
®
set to 0, the XTAL OSC will also
25MHz free running during VDD
Suspend (S-states). If this bit is
Output Enable (Disabling This
-Based Systems
output also disables the
be powered down in the
SATACLK is controlled
SATACLK is controlled
CPU/SRC/PCI outputs
CPU PLL M/N Enable
PCIEX1 is controlled
PCIEX2 is controlled
PCIEX1 is controlled
PCIEX0 is controlled
Enables Spread for
Control Function
Control Function
Control Function
Control Function
Freq Select Bit 4
Freq Select Bit 3
Freq Select Bit 2
Freq Select Bit 1
Freq Select Bit 0
Suspend States)
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
12.288M PLL).
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Reserved
Reserved
13
Type
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Does Not Run
Not Controlled
Not Controlled
Not Controlled
Not Controlled
Not Controlled
Not Controlled
See Table 1: CPU/SRC/PCI PLL
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Frequency Selection Table
Off
0
0
0
0
0.5% down spread
Controlled
Controlled
Controlled
Controlled
Controlled
Controlled
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Runs
1
1
1
1
1561A — 06/01/10
PWD
Latch
Latch
Latch
Latch
Latch
PWD
PWD
PWD
0
0
0
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
0
1
1
0
0
0
0
0
0