TP3057WM National Semiconductor, TP3057WM Datasheet - Page 3

• Manufacturer Part Number: TP3057WM
• Manufacturer: National Semiconductor
• Type: PCMr

Specifications of TP3057WM

• Number Of Channels: 1
• Gain Control: Adjustable
• Number Of Adc's: 1
• Number Of Dac's: 1
• Package Type: SOIC W
• Operating Supply Voltage (typ): ±5V
• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 1
• Operating Supply Voltage (max): ±5.25V
• Operating Supply Voltage (min): ±4.75V
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 16
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
POWER-UP
When power is first applied power-on reset circuitry initializ-
es the COMBO and places it into a power-down state All
non-essential circuits are deactivated and the D
outputs are put in high impedance states To power-up the
device a logical low level or clock must be applied to the
MCLK
ent Thus 2 power-down control modes are available The
first is to pull the MCLK
hold both FS
will power-down approximately 1 ms after the last FS
FS
pulse The TRI-STATE PCM data output D
the high impedance state until the second FS
SYNCHRONOUS OPERATION
For synchronous operation the same master clock and bit
clock should be used for both the transmit and receive di-
rections In this mode a clock must be applied to MCLK
and the MCLK
control A low level on MCLK
and a high level powers down the device In either case
MCLK
transmit and receive circuits A bit clock must also be ap-
plied to BCLK
select the proper internal divider for a master clock of 1 536
MHz 1 544 MHz or 2 048 MHz For 1 544 MHz operation
the device automatically compensates for the 193rd clock
pulse each frame
With a fixed level on the BCLK
selected as the bit clock for both the transmit and receive
directions Table 1 indicates the frequencies of operation
which can be selected depending on the state of BCLK
CLKSEL In this synchronous mode the bit clock BCLK
may be from 64 kHz to 2 048 MHz but must be synchro-
nous with MCLK
Each FS
data from the previous encode cycle is shifted out of the
enabled D
bit clock periods the TRI-STATE D
high impedance state With an FS
latched via the D
BCLK
MCLK
BCLK
Clocked
0
1
R
TABLE I Selection of Master Clock Frequencies
pulse Power-up will occur on the first FS
R
R
X
X R
if running) FS
will be selected as the master clock for both the
R
PDN pin and FS
X
X
pulse begins the encoding cycle and the PCM
CLKSEL
output on the positive edge of BCLK
X
X
and FS
R
X
and the BCLK
R
PDN pin can be used as a power-down
input on the negative edge of BCLK
R
X
R
inputs continuously low the device
and FS
X
1 536 MHz or
PDN pin high the alternative is to
and or FS
2 048 MHz
1 544 MHz
2 048 MHz
TP3057
R
R
Frequency Selected
R
R
PDN powers up the device
CLKSEL pin BCLK
must be synchronous with
CLKSEL can be used to
Master Clock
X
R
R
output is returned to a
pulses must be pres-
pulse PCM data is
X
1 536 MHz or
1 536 MHz or
1 544 MHz
2 048 MHz
1 544 MHz
X
will remain in
TP3054
X
pulse
and VF
X
X
X
or FS
After 8
will be
X
X
R
(or
R
or
O
X
R
X
3
ASYNCHRONOUS OPERATION
For asynchronous operation separate transmit and receive
clocks may be applied MCLK
2 048 MHz for the TP3057 or 1 536 MHz 1 544 MHz for the
TP3054 and need not be synchronous For best transmis-
sion performance however MCLK
with MCLK
logic levels to the MCLK
connect MCLK
Description) For 1 544 MHz operation the device automati-
cally compensates for the 193rd clock pulse each frame
FS
with MCLK
and must be synchronous with BCLK
clock the logic levels shown in Table 1 are not valid in
asynchronous mode BCLK
64 kHz to 2 048 MHz
SHORT FRAME SYNC OPERATION
The COMBO can utilize either a short frame sync pulse or a
long frame sync pulse Upon power initialization the device
assumes a short frame mode In this mode both frame sync
pulses FS
with timing relationships specified in Figure 2 With FS
during a falling edge of BCLK
BCLK
output the sign bit The following seven rising edges clock
out the remaining seven bits and the next falling edge dis-
ables the D
BCLK
of BCLK
edges latch in the seven remaining bits All four devices
may utilize the short frame sync pulse in synchronous or
asynchronous operating mode
LONG FRAME SYNC OPERATION
To use the long frame mode both the frame sync pulses
FS
with timing relationships specified in Figure 3 Based on the
transmit frame sync FS
short or long frame sync pulses are being used For 64 kHz
operation the frame sync pulse must be kept low for a mini-
mum of 160 ns The D
with the rising edge of FS
whichever comes later and the first bit clocked out is the
sign bit The following seven BCLK
the remaining seven bits The D
falling BCLK
FS
receive frame sync pulse FS
D
(BCLK
the long frame sync pulse in synchronous or asynchronous
mode
In applications where the LSB bit is used for signalling with
FS
lost LSB as ‘‘ ’’ to minimize noise and distortion
R
X
X
X
R
to be latched in on the next eight falling edges of BCLK
and FS
going low whichever comes later A rising edge on the
two bit clock periods long the decoder will interpret the
starts each encoding cycle and must be synchronous
X
R
X
enables the D
(BCLK
R
in synchronous mode) All four devices may utilize
latches in the sign bit The following seven falling
X
X
X
X
R
X
which is easily achieved by applying only static
and FS
and BCLK
output With FS
X
must be three or more bit clock periods long
edge following the eighth rising edge or by
X
in synchronous mode) the next falling edge
to all internal MCLK
R
X
X
must be one bit clock period long
TRI-STATE output buffer which will
X
TRI-STATE output buffer is enabled
X
R
FS
the COMBO will sense whether
X
X
PDN pin This will automatically
and BCLK
R
R
or the rising edge of BCLK
R
high during a falling edge of
starts each decoding cycle
X
will cause the PCM data at
X
X
R
output is disabled by the
the next rising edge of
X
and MCLK
should be synchronous
rising edges clock out
R
R
R
functions (see Pin
BCLK
may operate from
R
R
must be a
must be
X
high
X
R