IDTICS83948AYI01 IDT, Integrated Device Technology Inc, IDTICS83948AYI01 Datasheet
IDTICS83948AYI01
Specifications of IDTICS83948AYI01
Related parts for IDTICS83948AYI01
IDTICS83948AYI01 Summary of contents
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G D ENERAL ESCRIPTION The ICS83948I- low skew, 1-to-12 Differ- ,&6 ential-to-LVCMOS Fanout Buffer and a member HiPerClockS™ of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS83948I-01 has two selectable clock inputs. The CLK, ...
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ABLE IN ESCRIPTIONS ...
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BSOLUTE AXIMUM ATINGS Supply Voltage Inputs Outputs Package Thermal Impedance, JA Storage Temperature, Tstg Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings ...
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ABLE HARACTERISTICS ...
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P ARAMETER 1.65V±0.15V V DD, V DDO LVCMOS GND -1.65V±0.15V V DD nCLK CLK GND 83948AYI-01 D IFFERENTIAL M I EASUREMENT NFORMATION Qx 3. UTPUT OAD EST IRCUIT V Cross Points IFFERENTIAL ...
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Qx Qy PART 1 Qx PART 2 Qy 0.8V Clock Outputs 83948AYI-01 D IFFERENTIAL V DDO 2 V DDO 2 tsk( UTPUT KEW V DDO 2 V DDO 2 tsk(pp ART TO ART KEW ...
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LVCMOS_CLK nCLK CLK Q0:Q11 Q0:Q11 83948AYI-01 D IFFERENTIAL DDO ROPAGATION ELAY V V DDO DDO PERIOD t PW odc = t PERIOD t & ...
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W D IRING THE IFFERENTIAL Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V generated by the bias resistors R1, R2 and C1. This bias circuit should be ...
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ABLE VS IR LOW ABLE JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to ...
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ACKAGE UTLINE UFFIX ABLE ACKAGE ...
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ABLE RDERING NFORMATION ...