87354AMILFT IDT, Integrated Device Technology Inc, 87354AMILFT Datasheet
87354AMILFT
Specifications of 87354AMILFT
Related parts for 87354AMILFT
87354AMILFT Summary of contents
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G D ENERAL ESCRIPTION The ICS87354I is a high Differential-to-3.3V LVPECL Clock Generator. The CLK, nCLK pair can accept most standard differential input levels.The ICS87354I is characterized to operate from a 3.3V power supply. Guaranteed output and part-to-part skew characteristics ...
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ABLE IN ESCRIPTIONS ...
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BSOLUTE AXIMUM ATINGS Supply Voltage Inputs, V -0. Outputs Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, JA Storage Temperature, T -65°C to 150°C STG T 4A ...
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T 4D. LVPECL DC C ABLE HARACTERISTICS ...
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P ARAMETER LVPECL V EE -1.0V to -1.465V 3. UTPUT OAD EST IRCUIT PART 1 nQx Qx PART 2 nQy Qy t sk(pp ART TO ART KEW 80% ...
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IRING THE IFFERENTIAL NPUT TO Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V generated by the bias resistors R1, R2 and C1. This bias ...
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IFFERENTIAL LOCK NPUT NTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V SWING the V and V input requirements. Figures show PP CMR interface examples for ...
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T 3.3V LVPECL O ERMINATION FOR The clock layout topology shown below is a typical termi- nation for LVPECL outputs. The two different layouts men- tioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that ...
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This section provides information on power dissipation and junction temperature for the ICS87354I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS87354I is the sum of the core power plus the power ...
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Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4. F IGURE T o calculate worst case power dissipation into the ...
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ABLE VS IR LOW ABLE FOR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains ...
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ACKAGE UTLINE UFFIX FOR T ABLE Reference Document: JEDEC Publication 95, MS-012 87354AMI 3.3V LVPECL C SOIC EAD ACKAGE IMENSIONS ...
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ABLE RDERING NFORMATION ...
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We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of ...