ICS85102AGIT IDT, Integrated Device Technology Inc, ICS85102AGIT Datasheet

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ICS85102AGIT

Manufacturer Part Number
ICS85102AGIT
Description
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Driverr
Datasheet

Specifications of ICS85102AGIT

Number Of Clock Inputs
2
Output Frequency
500MHz
Output Logic Level
HCSL
Operating Supply Voltage (min)
2.97V
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.63V
Package Type
TSSOP
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
16
Lead Free Status / RoHS Status
Not Compliant
LOW SKEW, 1-TO-2, DIFFERENTIAL/LVCMOS-
TO-0.7V HCSL FANOUT BUFFER
B
IDT
G
input pair can accept most standard differential input levels.
The clock enable is internally synchronized to eliminate runt
clock pulses on the output during asynchronous assertion/
deassertion of the clock enable pin.
Guaranteed output and par t-to-par t skew characteristics
make the ICS85102I ideal for those applications demanding
well defined performance and repeatability.
CLK_SEL
HiPerClockS™
CLK_EN
IC S
nCLK0
LOCK
ENERAL
CLK0
CLK1
IREF
/ ICS
Pullup
Pulldown
Pullup/Pulldown
Pulldown
Pulldown
0.7V HCSL FANOUT BUFFER
D
The ICS85102I is a low skew, high performance 1-
to-2 Differential-to-HCSL fanout buffer and a mem-
ber of the HiPerClockS™ family of High Perfor-
mance Clock Solutions from IDT. The ICS85102I
has a differential clock input. The CLK0, nCLK0
IAGRAM
D
ESCRIPTION
0
1
D
LE
Q
Q0
nQ0
Q1
nQ1
1
F
Two 0.7V differential HCSL outputs
Selectable differential CLK0, nCLK0 or LVCMOS inputs
CLK0, nCLK0 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
CLK1 can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 500MHz
Translates any single-ended input signal to 3.3V
HCSL levels with resistor bias on nCLK input
Output skew: 65ps (maximum)
Part-to-part skew: 600ps (maximum)
Propagation delay: 3.2ns (maximum)
Additive phase jitter, RMS: 0.14ps typical @ 250MHz
3.3V operating supply
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
EATURES
P
4.4mm x 5.0mm x 0.925mm body package
IN
A
CLK_SEL
SSIGNMENT
CLK_EN
nCLK0
CLK0
CLK1
IREF
nc
nc
16-Lead TSSOP
ICS85102I
G Package
Top View
1
2
3
4
5
6
7
8
ICS85102AGI REV. A JUNE 10, 2008
16
15
14
13
12
11
10
9
GND
V
Q0
nQ0
Q1
nQ1
V
V
DD
DD
DD
ICS85102I

Related parts for ICS85102AGIT

ICS85102AGIT Summary of contents

Page 1

LOW SKEW, 1-TO-2, DIFFERENTIAL/LVCMOS- TO-0.7V HCSL FANOUT BUFFER G D ENERAL ESCRIPTION The ICS85102I is a low skew, high performance to-2 Differential-to-HCSL fanout buffer and a mem- HiPerClockS™ ber of the HiPerClockS™ family of High Perfor- mance ...

Page 2

ICS85102I LOW SKEW, 1-TO-2, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER ABLE IN ESCRIPTIONS ...

Page 3

ICS85102I LOW SKEW, 1-TO-2, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER T 3A ABLE ONTROL NPUT UNCTION ...

Page 4

ICS85102I LOW SKEW, 1-TO-2, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER BSOLUTE AXIMUM ATINGS Supply Voltage Inputs, V -0. Outputs Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, JA Storage Temperature, T ...

Page 5

ICS85102I LOW SKEW, 1-TO-2, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER 3.3V ± 10%, T ABLE HARACTERISTICS ...

Page 6

ICS85102I LOW SKEW, 1-TO-2, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using ...

Page 7

ICS85102I LOW SKEW, 1-TO-2, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER P ARAMETER 3.3V±10 HCSL 50 GND 475 IREF 0V This load condition is used for sk(o and t jit measurements HCSL O ...

Page 8

ICS85102I LOW SKEW, 1-TO-2, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER P ARAMETER Clock Period (Differential) Positive Duty Cycle (Differential) 0. IFFERENTIAL EASUREMENT OINTS FOR T STABLE V RB +150mV V = +100mV RB 0. ...

Page 9

ICS85102I LOW SKEW, 1-TO-2, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER ECOMMENDATIONS FOR NUSED I : NPUTS CLK I NPUT For applications not requiring the use of a clock input, it can be left floating. Though not required, but for ...

Page 10

ICS85102I LOW SKEW, 1-TO-2, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER IFFERENTIAL LOCK NPUT NTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V SWING input requirements. Figures show interface ...

Page 11

ICS85102I LOW SKEW, 1-TO-2, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER R T ECOMMENDED ERMINATION Figure 4A is the recommended termination for applications which require the receiver and driver separate PCB. All traces should be 50 impedance. Figure 4B ...

Page 12

ICS85102I LOW SKEW, 1-TO-2, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER This section provides information on power dissipation and junction temperature for the ICS85102I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85102I is the ...

Page 13

ICS85102I LOW SKEW, 1-TO-2, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 5. ...

Page 14

ICS85102I LOW SKEW, 1-TO-2, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER ABLE VS IR LOW ABLE FOR JA Multi-Layer PCB, JEDEC Standard Test Boards T C RANSISTOR OUNT The transistor count for ICS85102I is: 614 P P ...

Page 15

ICS85102I LOW SKEW, 1-TO-2, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER ABLE RDERING NFORMATION ...

Page 16

ICS85102I LOW SKEW, 1-TO-2, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications ...

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