EK43702-01 Peregrine Semiconductor, EK43702-01 Datasheet
EK43702-01
Specifications of EK43702-01
Related parts for EK43702-01
EK43702-01 Summary of contents
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... Excellent low-frequency performance 3 5.0 V Power Supply Voltage Fast switch settling time Programming Modes: Direct Parallel Latched Parallel Serial High-attenuation state @ power-up (PUP) CMOS Compatible No DC blocking capacitors required Packaged in a 24-lead 4x4x0.85 mm QFN RF Output P/S ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page ...
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... Frequency (MHz) ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 3 5 Frequency 9 kHz - 4 GHz 9 kHz - 4 GHz 9 kHz - 4 GHz 9 kHz - 4 GHz 9 kHz - 4 GHz 20 MHz - 4 GHz 20 MHz - 4 GHz 1MHz Figure 4. 0.25dB Attenuation vs. Attenuation State ...
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... Figure 10. Relative Phase vs. Frequency 1dB 2dB 31.75dB 140 120 100 Figure 12. Input IP3 vs. Frequency +85C ©2008-2009 Peregrine Semiconductor Corp. All rights reserved +25C 0dB 0.25dB 0.5dB 4dB 8dB 16dB Frequency (GHz) 0dB 0.25dB 0.5dB 1dB 4dB 8dB 16dB 31.75dB Frequency (GHz) 0dB 0.25dB 0.5dB ...
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... The PE43702 has a maximum 25 kHz switching rate. Switching rate is defined to be the speed at which the DSA can be toggled across attenuation states. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page Table 3. Operating Ranges Parameter Min V Power Supply Voltage 3 ...
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... Attenuation Word: Multiply by 4 and convert to binary → 12.5 dB → 50 → 00110010 Serial Input: 00110010 Document No. 70-0244-04 │ www.psemi.com Table 9. Serial Attenuation Word Truth Table Function Attenuation Setting D0 RF1-RF2 L Reference I. 31.75 dB LSB (first in Bit must be set to logic low ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Attenuation Word (LSB ...
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... Serial data is clocked in LSB first. The shift register must be loaded while LE is held LOW to prevent the attenuator value from changing ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data into the DSA ...
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... DISU T Parallel data hold time DIH T Parallel/Serial setup time PSSU T Parallel/Serial hold time PSIH Digital register delay T PD (internal) Digital register delay T DIPD (internal, direct mode only) ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Min Max Unit 100 - ns 100 - ns 100 - ns 100 - ...
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... Parallel is selected in the software. For manual latched-parallel programming, the procedure is identical to direct-parallel except now the LE pin on the Serial header must be logic low ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page Figure 17. Evaluation Board Layout Peregrine Specification 101-0310 Note: Reference Figure 18 for Evaluation Board Schematic as the parallel bits are applied ...
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... DSA 50 Ohm 4x4 MLP24 5 RF1 J4 6 GND Z=50 Ohm SMA 1 Note: Capacitors C1-C8, C13, & C14 may be omitted. SERIAL HEADER 4 CLK 1 CLOCK DATA 2 DATA GND CLK GND J5 14 RF2 SMA 13 1 GND Z=50 Ohm ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page ...
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... Figure 20. Tape and Reel Drawing Figure 21. Marking Specifications 43702 YYWW ZZZZZ Table 12. Ordering Information Order Code Part Marking PE43702MLI 43702 PE43702MLI-Z 43702 PE43702 G – 24QFN 4x4mm-3000C EK43702-01 43702 ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page Tape Feed Direction 1.1 ...
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... Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS, HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp. ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page ...