HI-8588PSI-10 Holt Integrated Circuits, HI-8588PSI-10 Datasheet - Page 2

• Manufacturer Part Number: HI-8588PSI-10
• Manufacturer: Holt Integrated Circuits

Specifications of HI-8588PSI-10

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: SOIC N
• Rad Hardened: No
• Lead Free Status / RoHS Status: Not Compliant

FUNCTIONAL DESCRIPTION
RECEIVER
Figure 1 shows the general architecture of the ARINC 429
receiver. The receiver operates off the VCC supply only.
The inputs RINA and RINB each require 35K
tance of which 25K is internal to the chip. The series re-
sistance is connected to level translators whose resistance
to Ground is typically 10K . In order for the voltage trans-
lation not to be adversely affected, an external 10K series
resister must be added to each ARINC input.
HI-8588-10 device is typically chosen for applications
where external series resistors are required in its lightning
protection circuitry.
After level translation, the inputs are buffered and become
inputs to a differential amplifier. The amplitude of the differ-
ential signal is compared to levels derived from a divider
APPLICATION INFORMATION
Figure 2 shows a possible application of the
HI-8588-10 interfacing an ARINC receive
channel to the HI-6010 which in turn inter-
faces to an 8-bit bus.
RINA
RINB
TRANSLATION
PROTECTION
AND
ESD
FIGURE 1 - RECEIVER BLOCK DIAGRAM
FIGURE 2 - APPLICATION DIAGRAM
HOLT INTEGRATED CIRCUITS
Channel
Channel
of resis-
ARINC
ARINC
DRIVE FROM LOGIC
HARDWIRE
HI-8588-10
The
OR
ZERO
NULL
NULL
ONE
2
{
between VCC and Ground. The nominal settings corre-
spond to a One/Zero amplitude of 6.0V and a Null ampli-
tude of 3.3V.
The status of the ARINC receiver input is latched. A Null
input resets the latches and a One or Zero input sets the
latches.
The logic at the output is controlled by the test signal
which is generated by the logical OR of the TESTA and
TESTB pins. Unlike the HI-8588, if TESTA and TESTB
are both One, the HI-8588-10 outputs are pulled low in-
stead of being tri-stated. This allows the digital outputs
of a transmitter to be connected to the test inputs through
control logic for self-test purposes.
S
R
S
R
LATCH
LATCH
8
6
7
2
4
3
Q
Q
TXAOUT
TESTA
TESTB
RINA
RINB
TXBOUT
HI-8588-10
4
HI-8586
GND
1
SLP1.5
5
GND
5V
VCC
TESTB
TESTB
TESTA
TESTA
-15V
1
15V
5
TEST
TEST
V-
V+
ROUTB
ROUTA
TX0IN
TX1IN
8
6
7
3
2
RXD1
RXD0
TXD1
TXD0
HI-6010
8 BIT BUS
ROUTA
ROUTB