COM20020ILJP Standard Microsystems (SMSC), COM20020ILJP Datasheet
COM20020ILJP
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COM20020ILJP Summary of contents
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... On-Chip Dual Port RAM Command Chaining for Packet Queuing Sequential Access to Internal RAM Software Programmable Node ID COM20020ILJP for 28 pin PLCC package COM20020I-DZD for 28 pin PLCC lead-free RoHS compliant package COM20020I-HD for 48 pin TQFP package COM20020I-HT for 48 pin TQFP lead-free RoHS compliant package ...
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Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123 Copyright © 2006 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet Table of Contents Chapter 1 General Description................................................................................................................ 6 Chapter 2 Pin Configurations .................................................................................................................. 7 Chapter 3 Description of Pin Functions .................................................................................................. 9 Chapter 4 Protocol Description ............................................................................................................. 12 ...
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Improved Diagnostics.................................................................................................................................48 6.8.1 Normal Results:...................................................................................................................................48 6.8.2 Abnormal Results:...............................................................................................................................48 6.9 Oscillator ....................................................................................................................................................49 Chapter 7 Operational Description........................................................................................................ 50 7.1 Maximum Guaranteed Ratings* .................................................................................................................50 7.2 DC Electrical Characteristics......................................................................................................................50 Chapter 8 Timing Diagrams .................................................................................................................. 53 Chapter 9 Package Outlines ................................................................................................................. 66 Appendix A.................................................................................................................................................. ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet Table 6.10 - Setup 1 Register .......................................................................................................................................36 Table 6.11 - Setup 2 Register .......................................................................................................................................37 Table 9 Pin TQFP Package Parameters ............................................................................................................67 For more details on the ...
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Chapter 1 General Description SMSC's COM20020ID is a member of the family of Embedded ARCNET Controllers from Standard Microsystems Corporation. The device is a general purpose communications controller for networking microcontrollers and intelligent peripherals in industrial, automotive, and embedded control ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet Chapter 2 Pin Configurations nWR/DIR 26 nRD/nDS 27 28 VDD A0/nMUX A2/ALE 3 AD0 Ordering Information: COM20020 I LJP PACKAGE TYPE: "LJP" = Standard (Sn/Pb) ...
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AD0 1 AD1 2 N/C 3 AD2 4 N/C 5 VSS VDD VSS Figure 2.2 - Pin Configuration - COM20020I 48-Pin TQFP Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet Chapter 3 Description of Pin Functions PLCC PIN NAME NO. 1-3 Address 0-2 4-6,8-12 Data 0-7 27 nRead/nData Strobe 26 nWrite/ Direction 23 nReset in 24 nInterrupt 25 ...
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PLCC PIN NAME NO. 21 nTransmit nEnable 16,17 Crystal Oscillator 15,28 Power Supply 7,14,22 Ground Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM SYMBOL nTXEN Output. This signal is used prior to the Power-up to ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet Reconfigure Timer has Timed Out Start Reconfiguration Timer (420 mS TA? Transmit Transmit Broadcast Send Packet Y Was Packet Broadcast Activity ...
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Chapter 4 Protocol Description 4.1 Network Protocol Communication on the network is based on a token passing protocol. Establishment of the network configuration and management of the network protocol are handled entirely by the COM20020ID's internal microcoded sequencer. A processor ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet CKUP1 CKUP0 This clock multiplier is powered-down (bypassed) on default. After changing the CKUP1 and CKUP0 bits, the ARCNET core operation is stopped and ...
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Broadcast Messages Broadcasting gives a particular node the ability to transmit a data packet to all nodes on the network simultaneously. ID zero is reserved for this feature and no node on the network can be assigned ID zero. ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet each result, one byte is transmitted every 2.2 μS and the time to transmit a message can be precisely determined. The line idles in a spacing ...
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Acknowledgements An Acknowledgement is used to acknowledge reception of a packet affirmative response to FREE BUFFER ENQUIRIES and is sent by the following sequence: An ALERT BURST An ACK (ACKnowledgement--ASCII code 86H) character 4.6.5 Negative Acknowledgements ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet Chapter 5 System Description 5.1 Microcontroller Interface The top halves of Figure 5.1 and Figure 5.2 illustrate typical COM20020ID interfaces to the microcontrollers. The interfaces consist of a ...
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XTAL1 XTAL2 AD0- ALE A15 RESET nRD nWR nINT1 8051 RXIN TXEN nPULSE nPULSE GND BACKPLANE FIGURE A Figure 5.1 – Multiplexed, 8051-Like Bus Interface with RS-485 Interface Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet XTAL1 XTAL2 D0- nRES nIOS R/nW nIRQ1 6801 RXIN nTXEN nPULSE1 nPULSE2 GND Figure 5.2 – Non-Multiplexed, 6801-Like Bus Interface with RS-485 Interface SMSC ...
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High Speed CPU Bus Timing Support High speed CPU bus support was added to the COM20020ID. The reasoning behind this is as follows: With the Host interface in Non-multiplexed Bus mode, I/O address and Chip Select signals must be ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet In the MOTOROLA CPU mode (DIR, nDS mode), the same modifications apply. RBUSTMG BIT 0 1 5.2 Transmission Media Interface The bottom halves of Figure 5.1 and Figure ...
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The nPULSE1 signal, in this mode open drain or push/pull driver and is used to directly drive the media. It issues a 200nS negative pulse to transmit a logic "1". Note that ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet of the receive signal (like filtering or squelching), nPULSE1 and RXIN remain as independent pins. External differential drivers/receivers for increased range and common mode noise rejection, for example, ...
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ADDRESS DECODING CIRCUITRY AD0-AD2, D3-D7 nINTR RESET nRESET LOGIC nRD/nDS nWR/DIR BUS ARBITRATION nCS CIRCUITRY CABLE TYPE RG-62 Belden #86262 RG-59/U Belden #89108 RG-11/U Belden #89108 IBM Type 1* Belden #89688 IBM Type 3* Telephone Twisted Pair Belden #1155A COMCODE ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet Note: For more detailed information on Cabling options including RS-485, transformer-coupled RS-485 and Fiber Optic interfaces, please refer to TN7-5 – Cabling Guidelines for the COM20020 ULANC, available ...
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Chapter 6 Functional Description 6.1 Microsequencer The COM20020ID contains an internal microsequencer which performs all of the control operations necessary to carry out the ARCNET protocol. It consists of a clock generator, a 544 x 8 ROM, a program counter, ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet Note 6.1 (R/W) This bit can be Written or Read. For more information see Appendix C - Identification of the COM20020 Rev B, Rev C and Rev D. ...
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New Next ID interrupt is cleared by reading the Next ID Register. The Interrupt Mask Register defaults to the value 0000 0000 upon hardware reset. 6.2.2 Data Register This read/write 8-bit register is used as the channel through which the ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet 6.2.6 Status Register The COM20020ID Status Register is an 8-bit read-only register. All of the bits, except for bits 5 and 6, are software compatible with previous SMSC ...
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Setup 1 Register The Setup 1 Register is a read/write 8-bit register accessed when the Sub Address Bits are set up accordingly (see the bit definitions of the Configuration Register). The Setup 1 Register allows the user to change ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet BIT BIT NAME SYMBOL 7 Receiver RI Inhibited 6,5 (Reserved) 4 Power On Reset POR 3 Test TEST 2 Reconfiguration RECON 1 Transmitter TMA Message Acknowledged 0 Transmitter ...
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BIT BIT NAME SYMBOL 7 My Reconfiguration MY- RECON 6 Duplicate ID DUPID 5 Receive RCVACT Activity 4 Token Seen TOKEN 3 Excessive NAK EXCNAK 2 Tentative ID TENTID 1 New Next ID NEW NXTID 1,0 (Reserved) Revision 12-05-06 5Mbps ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet DATA COMMAND 0000 0000 Clear Transmit Interrupt 0000 0001 Disable Transmitter 0000 0010 Disable Receiver b0fn n100 Enable Receive to Page fnn 00fn n011 Enable Transmit from Page ...
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BIT BIT NAME SYMBOL 7 Read Data RDDATA 6 Auto Increment AUTOINC 5-3 (Reserved) 2-0 Address 10-8 A10-A8 BIT BIT NAME SYMBOL 7-0 Address 7-0 A7-A0 BIT BIT NAME SYMBOL 7-3 Reserved 2,1,0 Sub Address 2,1,0 SUBAD 2,1,0 Revision 12-05-06 ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet BIT BIT NAME SYMBOL 7 Reset RESET 6 Command CCHEN Chaining Enable 5 Transmit Enable TXEN 4,3 Extended ET1, ET2 Timeout 1,2 2 Backplane BACK- PLANE 1,0 Sub ...
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BIT BIT NAME SYMBOL 7 Pulse1 Mode P1MODE 6 Four NACKS FOUR NACKS 5 Reserved 4 Receive All RCVALL 3,2,1 Clock Prescaler Bits CKP3,2,1 3,2,1 0 Slow Arbitration SLOWARB Select Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller with 2K x ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet BIT BIT NAME SYMBOL 7 Read Bus Timing RBUSTMG Select 6 Reserved 5,4 Clock Multiplier CKUP1 Enhanced Functions Synchronous NOSYNC SMSC COM20020I Rev ...
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BIT BIT NAME SYMBOL 1,0 RCNTM1,0 Reconfiguration Timer 1, 0 Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM DESCRIPTION These bits are used to program the reconfiguration timer as a function of maximum node count. ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet D0-D7 I/O Address 02H SMSC COM20020I Rev D Data Register I/O Address 04H Memory Data Bus 8 Address Pointer Register I/O Address 03H High Low Memory Address Bus ...
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Internal RAM The integration of the RAM in the COM20020ID represents significant real estate savings. The most obvious benefit is the 48 pin package in which the device is now placed (a direct result of the ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet The software flow for controlling the Configuration, Node ID, Tentative ID, and Next ID registers is generally limited to the initialization sequence and the maintenance of the network ...
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ADDRESS COUNT 255 511 N = DATA PACKET LENGTH SID = SOURCE ID DID = DESTINATION ID (DID = 0 FOR BROADCASTS) Figure 6.2 - RAM Buffer Packet Configuration 6.4.2 Transmit Sequence During a transmit sequence, the ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet number of information bytes in the message. The SID in Address 0 is used by the receiving node to reply to the transmitting node. The COM20020ID puts the ...
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Receive Sequence A receive sequence begins with the RI status bit becoming a logic "1", which indicates that a previous reception has concluded. The microcontroller will be interrupted if the corresponding bit in the Interrupt Mask Register is set ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet 6.5 Command Chaining The Command Chaining operation allows consecutive transmissions and receptions to occur without host microcontroller intervention. Through the use of a dual two-level FIFO, commands to ...
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When the token is received again, the second transmission will be automatically initiated after the first is completed by using the stored "Enable Transmit from Page fnn" command. The operation new "Enable Transmit from Page fnn" ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet 6.6 Reset Details 6.6.1 Internal Reset Logic The COM20020ID includes special reset circuitry to guarantee smooth operation during reset. Special care is taken to assure proper operation in ...
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The Tentative ID Register may be used to build a network map of all the nodes on the network, even once the COM20020ID has joined the network. Once a value is placed in the Tentative ID Register, the COM20020ID looks ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet RCVACT=0, TOKEN=0, TXEN=1: No receive activity is seen and the basic transmit function is enabled. The transmitter and/or receiver are not functioning properly. RCVACT=0, TOKEN=0, TXEN=0: No receive ...
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Chapter 7 Operational Description 7.1 Maximum Guaranteed Ratings* Operating Temperature Range .................................................................................................. 0 Storage Temperature Range ................................................................................................-55 Lead Temperature (soldering, 10 seconds) ....................................................................................... +325 Positive Voltage on any pin, with respect to ground ........................................................................V Negative Voltage on any pin, with ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet PARAMETER Low Output Voltage 1 (nPULSE1 in Push/Pull Mode, nPULSE2, NTXEN) High Output Voltage 1 (nPULSE1 in Push/Pull Mode, nPULSE2, nTXEN) Low Output Voltage 2 (D0-D7) High Output ...
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CAPACITANCE (T = 25° Output and I/O pins capacitive load specified as follows: PARAMETER SYMBOL Input Capacitance Output Capacitance 1 C (All outputs except XTAL2, nPULSE1 in Push/Pull Mode) Output Capacitance 2 C (nPULSE1, in BackPlane Mode Only ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet Chapter 8 Timing Diagrams AD0-AD2, D3-D7 nCS t11 ALE nDS DIR t1 Address Setup to ALE Low t2 Address Hold from ALE Low t3 nCS Setup to ALE ...
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AD0-AD2, D3-D7 t1 nCS ALE t9 nRD nWR t1 Address Setup to ALE Low t2 Address Hold from ALE Low t3 nCS Setup to ALE Low t4 nCS Hold from ALE Low t5 ALE Low to nRD Low t6 nRD ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet AD0-AD2, D3-D7 t1 nCS t11 ALE nDS DIR t1 Address Setup to ALE Low Address Hold from ALE Low t2 nCS Setup to ALE Low t3 nCS Hold ...
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AD0-AD2, VALID D3-D7 t1 nCS t3 t9 ALE nWR nRD t13 t1 Address Setup to ALE Low Address Hold from ALE Low t2 nCS Setup to ALE Low t3 nCS Hold from ALE Low t4 ALE Low to nDS Low ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet A0-A2 nCS nRD nWR D0-D7 t1 Address Setup to nRD Active Address Hold from nRD Inactive t2 nCS Setup to nRD Active t3 nCS Hold from nRD Inactive ...
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A0-A2 nCS Note 3 nRD nWR D0-D7 t1 Address Setup to nRD Active Address Hold from nRD Inactive t2 nCS Setup to nRD Active t3 nCS Hold from nRD Inactive t4 Cycle Time (nRD Low to Next Time Low) t5 ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet A0-A2 nCS DIR nDS D0-D7 t1 Address Setup to nDS Active t2 Address Hold from nDS Inactive t3 nCS Setup to nDS Active t4 nCS Hold from nDS ...
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A0-A2 nCS DIR nDS D0-D7 t1 Address Setup to nDS Active t2 Address Hold from nDS Inactive t3 nCS Setup to nDS Active t4 nCS Hold from nDS Inactive t5 DIR Setup to nDS Active t6 Cycle Time (nDS Low ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet A0-A2 nCS Note 3 nRD nWR D0-D7 Parameter t1 Address Setup to nWR Active t2 Address Hold from nWR Inactive t3 nCS Setup to WR Active nCS Hold ...
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A0-A2 nCS DIR nDS D0-D7 Parameter t1 Address Setup to nDS Active t2 Address Hold from nDS Inactive t3 nCS Setup to nDS Active t4 nCS Hold from nDS Inactive t5 DIR Setup to nDS Active t6 Cycle Time (nDS ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet nTXEN t4 t1 nPULSE1 nPULSE2 t6 RXIN Parameter t1 nPULSE1, nPULSE2 Pulse Width t2 nPULSE1, nPULSE2 Period t3 nPULSE1, nPULSE2 Overlap t4 nTXEN Low to nPULSE1 Low t5 ...
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Clk) RXIN nPULSE2 High to nTXEN Low t1 t2 nPULSE1 Pulse Width t3 nPULSE1 Period t4 nPULSE2 Low to nPULSE1 Low t5 nPULSE2 High Time t6 nPULSE2 Low Time t7 nPULSE2 Period t8 nPULSE2 ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet t1 4.0V XTAL1 Parameter t1 Input Clock High Time t2 Input Clock Low Time t3 Input Clock Period t4 Input Clock Frequency t5 Frequency Accuracy* Note*: Input clock ...
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Chapter 9 Package Outlines OTES dim ensions are in inches ircle indicating pin 1 can appear on a top surface as show n on the draw ing or right above it ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet Table 9 Pin TQFP Package Parameters MIN NOMINAL 0.05 A2 1.35 D 8.80 D/2 4.40 D1 6.90 E 8.80 E/2 4.40 E1 6.90 ...
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Appendix A This appendix describes the function of the NOSYNC and EF bits. NOSYNC Bit The NOSYNC bit controls whether or not the RAM initialization sequence requires the line to be idle by enabling or disabling the SYNC command during ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet synchronized between the CPU and COM20020ID. Thus, changing the CKP3-1 timing does not synchronize with the internal clocks of Pre-Scalar, and changing CKP3-1 may cause spike noise to ...
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EF=0 TA/RI bit Setting Pulse nINTR pin EF=1 TA/RI bit Setting Pulse nINTR pin Figure 0.1 - Effect of the EF Bit on the TA/RI Bit Revision 12-05-06 5Mbps ARCNET (ANSI 878.1) Controller with On-Chip RAM Tx/Rx ...
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ARCNET (ANSI 878.1) Controller with On-Chip RAM Datasheet Appendix B - Example of Interface Circuit Diagram to ISA Bus ISA Bus AEN nG SA15-SA4 P 12 SD7-SD0 A 8 nIOR nIOW SA2-SA0 3 IRQm nIOCS16 DRQn ...
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Appendix C - Software Identification of the COM20020 Rev B, Rev C and Rev D In order to properly write software to work with the COM20020 Rev B, C and necessary to be able to identify the ...