ICS830S21AMI IDT, Integrated Device Technology Inc, ICS830S21AMI Datasheet
ICS830S21AMI
Specifications of ICS830S21AMI
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ICS830S21AMI Summary of contents
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... Full 3.3V and 2.5V operating supply • -40°C to 85°C ambient operating temperature • Available in lead-free (RoHS 6) package Pin Assignment nc 1 CLK 2 nCLK ICS830S21I 8-Lead SOIC 3.9mm x 4.9mm x 1.375mm package body M Package Top View 1 ICS830S21AMI REV. A MARCH 21, 2008 ICS830S21I GND 5 ...
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... Non-inverting differential clock input. Pulldown Pullup/ Inverting differential clock input. Pulldown Output reference voltage. Power supply ground. Single-ended clock output. LVCMOS / LVTTL interface levels. Positive supply pin. Test Conditions V = 3.465V 2.625V 3. 2. Minimum Typical Maximum ICS830S21AMI REV. A MARCH 21, 2008 Units pF Ω k Ω Ω Ω ...
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... See Parameter Measurement Information, Output Load Test Circuit diagrams 0.5V + 0.5V Minimum Typical Maximum 3.135 3.3 3.465 12 Minimum Typical Maximum 2.375 2.5 2.625 11 = -40°C to 85°C A Minimum Typical Maximum 2.6 1.8 0.5 ICS830S21AMI REV. A MARCH 21, 2008 Units V mA Units V mA Units ...
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... IN 0.15 GND + 0.5 V – 1.4 V – 1 Minimum Typical 350 0.95 0. /2. DD /2. Minimum Typical 350 1 0.11 125 47 /2. DD /2. ICS830S21AMI REV. A MARCH 21, 2008 Maximum Units 150 µA µA 1 – 0. – 1 Maximum Units MHz 1.95 ns 525 500 Maximum Units MHz ...
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... Additive Phase Jitter @ 350MHz 12kHz to 20MHz = 0.11ps (typical) Offset Frequency (Hz) This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. 5 ICS830S21AMI REV. A MARCH 21, 2008 ...
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... PERIOD Output Duty Cycle/Pulse Width/Period IDT™ / ICS™ LVCMOS/LVTTL TRANSLATOR SCOPE Qx LVCMOS -1.25V±5% 2.5V Core/2.5V LVCMOS Output Load AC Test Circuit nCLK CLK V CMR Propagation Delay x 100% Output Rise/Fall Time 6 1.25V± GND 80% 20 ICS830S21AMI REV. A MARCH 21, 2008 SCOPE Qx 80% 20 ...
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... For example, if the input clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V and DD R2/R1 = 0.609. IDT™ / ICS™ LVCMOS/LVTTL TRANSLATOR / Single Ended Clock Input Figure 1. Single-Ended Signal Driving Differential Input CLK V_REF nCLK C1 0. ICS830S21AMI REV. A MARCH 21, 2008 ...
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... Zo = 50Ω R1 100 Zo = 50Ω LVDS Driven by a 3.3V LVDS Driver 2. 120 120 Zo = 60Ω 60Ω SSTL R1 R2 120 120 Driven by a 2.5V SSTL Driver ICS830S21AMI REV. A MARCH 21, 2008 3.3V CLK nCLK HiPerClockS Input 3.3V CLK nCLK Receiver 3.3V CLK nCLK HiPerClockS ...
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... All Dimensions in Millimeters Symbol Minimum N A 1.35 A1 0.10 B 0.33 C 0.19 D 4. 5.80 h 0.25 L 0.40 α 0° Reference Document: JEDEC Publication 95, MS-012 9 2.5 79.6°C/W Maximum 8 1.75 0.25 0.51 0.25 5.00 4.00 1.27 Basic 6.20 0.50 1.27 8° ICS830S21AMI REV. A MARCH 21, 2008 ...
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... IDT™ / ICS™ LVCMOS/LVTTL TRANSLATOR Package Shipping Packaging “Lead-Free” 8 Lead SOIC “Lead-Free” 8 Lead SOIC 2500 Tape & Reel 10 Temperature Tube -40°C to 85°C -40°C to 85°C ICS830S21AMI REV. A MARCH 21, 2008 ...
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ICS830S21I 1-TO-1, 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 ...