HD74ACT283RP Renesas Electronics America, HD74ACT283RP Datasheet - Page 4

HD74ACT283RP

Manufacturer Part Number
HD74ACT283RP
Description
Manufacturer
Renesas Electronics America
Datasheet

Specifications of HD74ACT283RP

Logic Family
ACT
Logical Function
Binary Full Adder
Technology
CMOS
Number Of Elements
1
Number Of Bits
4
Propagation Delay Time
16.5ns
High Level Output Current
-24mA
Low Level Output Current
24mA
Operating Supply Voltage (typ)
5V
Operating Temp Range
-40C to 85C
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Quiescent Current
8uA
Pin Count
16
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Not Compliant
HD74AC283/HD74ACT283
Logic Symbol
Pin Names
Functional Description
The HD74AC283/HD74ACT283 adds two 4-bit binary words (A plus B) plus the incoming Carry (C
The binary sum appears on the Sum (S
various inputs and outputs is indicated by the subscript numbers, representing powers of two.
Interchanging inputs of equal weight does not affect the operation. Thus C
assigned to pins 5, 6 and 7 for DIPS.
HD74AC283/HD74ACT283 can be used either with all inputs and outputs active High (positive logic) or
with all inputs and outputs active Low (negative logic). See Figure a. Note that if C
tied Low for active High logic or tied High for active Low logic.
Due to pin limitations, the intermediate carries of the HD74AC283/HD74ACT283 are not brought out for
use as inputs or outputs. However, other means can be used to effectively insert a carry into, or bring a
carry out from, an intermediate stage. Figure b shows how to make a 3-bit adder. Tying the operand inputs
of the fourth adder (A
Using somewhat the same principle Figure c shows a way of dividing the HD74AC283/HD74ACT283 into
a 2-bit and a 1-bit adder. The third stage adder (A
(C
Note that as long as A
when A
2
10
A
B
C
S
C
2
Where (+) = plus
) signal into the fourth stage (via A
0
0
0
0
0
4
(A
– S
– A
– B
2
0
3
and B
+ B
3
3
0
A Operand Inputs
B Operand Inputs
Carry Input
Sum Outputs
Carry Output
+ C
2
are the same the carry into the third stage does not influence the carry out of the third
0
) + 2
3
, B
2
1
and B
(A
3
) Low makes S
1
+ B
2
are the same, whether High or Low, they do not influence S
C
1
) + 2
0
A
0
2
S
(A
0
2
0
B
– S
3
and B
2
0
dependent only on, and equal to, the carry from the third adder.
+ B
3
) and outgoing carry (C
A
Due to the symmetry of the binary add function, the
1
2
S
2
) + 2
) and bringing out the carry from the second stage on S
1
B
1
2
3
, B
(A
A
2
2
S
3
, S
2
+ B
B
2
2
) is used merely as a means of getting a carry
3
) = S
A
3
S
3
0
B
+ 2S
3
4
) outputs. The binary weight of the
C
4
1
+ 4S
2
0
, A
+ 8S
0
, B
0
3
is not used it must be
+ 16C
0
can be arbitrarily
4
2
. Similarly,
0
).
2
.

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