CG7C324A15JC Cypress Semiconductor Corp, CG7C324A15JC Datasheet
CG7C324A15JC
Specifications of CG7C324A15JC
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CG7C324A15JC Summary of contents
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... MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL I/O I/O I Cypress Semiconductor Corporation Document #: 38-03012 Rev. ** Reprogrammable Asynchronous — • High reliability — Proven EPROM technology — >2001V input protection — 100% programming and functional testing • Windowed DIP, windowed LCC, DIP, LCC, PLCC avail- able ...
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Selection Guide Generic Part Number Com‘l Mil 20RA10-15 15 20RA10- 20RA10-25 25 20RA10-35 35 Pin Configurations LCC Top View 282726 I ...
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Output Always Enabled External Pin OE Figure 2. Four Possible Output Enable Alternatives for the PLDC20RA10 Document #: 38-03012 Rev. ** PRELOAD (FROM PIN Figure 1. PLDC20RA10 Macrocell RA10–6 Combination of ...
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Registered/ActiveLOW Registered/Active HIGH Figure 3. Four Possible Macrocell Configurations for the PLDC20RA10 Document #: 38-03012 Rev RA10–10 RA10–12 PLDC20RA10 Combinatorial/Active LOW RA10–11 Combinatorial/Active HIGH RA10–13 Page ...
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Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. – +150 C Ambient Temperature with Power Applied............................................. – +125 C Supply Voltage to Ground Potential (Pin ...
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AC Test Loads and Waveforms (Commercial) R1 457 (470 MIL) 5V OUTPUT OUTPUT R2 270 50 pF (319 Mil) INCLUDING JIG AND SCOPE (a) Equivalent to: THÉ VENIN EQUIVALENT(Commercial) 170 OUTPUT Parameter 1.5V PXZ(–) t 2.6V PXZ(+) ...
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Switching Characteristics Over the Operating Range Parameter Description t Input or Feedback to PD Non-Registered Output t Input to Output Enable EA t Input to Output ER Disable t Pin 13 to Output PZX Enable t Pin 13 to Output ...
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Switching Waveform INPUTS,REGISTERED FEEDBACK CP ASYNCHRONOUS RESET ASYNCHRONOUS SET t PD OUTPUTS (HIGHASSERTED) OUTPUT ENABLE INPUTPIN Preload Switching Waveform PIN 13 OUTPUT ENABLE REGISTER OUTPUTS PIN 1 PRELOAD CLOCK Asynchronous Reset ASYNCHRONOUS RESET OUTPUT Asynchronous Set ASYNCHRONOUS SET OUTPUT Document ...
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Functional Logic Diagram Document #: 38-03012 Rev. ** PLDC20RA10 Page ...
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Ordering Information (ns) (ns) (ns) CC2 PLDC20RA10-15JC PLDC20RA10-15PC CG7C324-A15JC PLDC20RA10-20PC CG7C324-A20JC PLDC20RA10-20DMB PLDC20RA10-20WMB PLDC20RA10-25DMB PLDC20RA10-25WMB PLDC20RA10-35DMB ...
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Package Diagrams 24-Lead (300-Mil) CerDIP D14 MIL-STD-1835 D- 9Config.A 28-Square L64 Carrier Chip MIL-STD-1835 C-4 Document #: 38-03012 Rev. ** 28-Lead Plastic Leaded Chip Carrier J64 Leadless 28-Pin Windowed Leadless Chip Carrier Q64 PLDC20RA10 MIL-STD-1835 C-4 Page ...
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Package Diagrams (continued) Document #: 38-03012 Rev. ** 28-Pin Windowed Leaded Chip Carrier H64 PLDC20RA10 Page ...
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... Document #: 38-03012 Rev. ** © Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...
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Document Title: PLDC20RA10 Reprogrammable Asynchronous CMOS Logic Device Document Number: 38-03012 REV. ECN NO. Issue Date ** 106294 04/24/01 Document #: 38-03012 Rev. ** Orig. of Change SZV Change from Spec number: 38-00073 to 38-03012 PLDC20RA10 Description of Change Page ...