PNX1301EH NXP Semiconductors, PNX1301EH Datasheet - Page 132

• Manufacturer Part Number: PNX1301EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1301EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
Graphics Overlay
The graphics overlay is enabled by the VO_CTL. OL_EN
bit. The graphics overlay is typically a software-generat-
ed graphic overlaid onto the output video image stream.
The graphics overlay is either generated in YUV by the
DSPCPU or converted by the DSPCPU from an RGB to
a YUV overlay image. Because RGB-to-YUV conversion
can potentially lose information, this conversion is done
by the DSPCPU, because it has the most information
about how best to perform this conversion in the most ef-
fective manner.
The overlay height should be chosen such that the over-
lay does not vertically extend beyond the image area. A
height greater than this causes undefined results and
may result in vertical overlay wraparound.
Note: The emitted byte data rate is limited to 45% of the
SDRAM clock when overlays are enabled.
The YUV overlay logic assembles the U0, Y0, V0, Y1
bytes for a pair of YUV 4:2:2 pixels for both the main im-
age and the overlay image. The alpha bit for pixel 0 (the
LSB of the U0 byte of the overlay image) selects
ALPHA_ZERO or ALPHA_ONE as the alpha source,
and the alpha blend logic combines U0, Y0, and V0 from
the main and overlay images to generate the U0, Y0 and
V0 output values. The alpha bit for pixel 1 (the LSB of the
V0 byte of the overlay image) selects ALPHA_ZERO or
ALPHA_ONE as the alpha source for blending the Y1
pixels to generate the Y1 output value. The alpha blend-
ed U0, Y0, V0 and Y1 bytes are sent to the EVO output
Figure 7-31. EVO frame timing.
7-22
264
266
283
525
20
1
4
PRELIMINARY SPECIFICATION
Blanking: Field 2 Overlap
Blanking: Field 1 Overlap
Video Image: Field 1
Video Image: Field 2
Blanking: Field 2
Blanking: Field 1
525 Line / 60 Hz
port in the YUV 422 sequence. The overlay U and V val-
ues used assume an LSB of zero.
Video Image Addressing
The output image is read from SDRAM at a location de-
fined by Y_BASE_ADR, Y_OFFSET, U_BASE_ADR,
U_OFFSET, V_BASE_ADR, and V_OFFSET. The de-
fault memory packing is big-endian although little-endian
packing is also supported by setting the VO_CTL.
LTL_END bit.
Horizontally-adjacent samples are stored at successive
byte addresses, resulting in a packed form (four 8-bit
samples are packed into one 32-bit word). Upon horizon-
tal retrace, the starting byte address for the next line is
computed by adding the corresponding offset value to
the previous line’s starting byte address. Note that
{OL,Y,U,V}_OFFSET values are 16-bit unsigned quanti-
ties. This process continues until the total image—height
in lines and width in pixels per line—has been read from
memory for luminance (Y). For chrominance, the same
number of lines are read, but half the number of pixels
per line are read in YUV 4:2:2 and YUV 4:2:0 formats
The YUV 4:2:0 format has half the number of U and V
lines in memory that the YUV 4:2:2 formats have, but
each line of U and V data is read and used twice. See
Figure 7-19
1.
311
313
336
623
624
625
Note that consecutive pixel components of each line
are stored in consecutive memory addresses but con-
secutive lines need not be in consecutive memory ad-
dresses
23
1
through
Blanking: Field 1 Overlap
Blanking: Field 2 Overlap
Video Image: Field 2
Video Image: Field 1
Blanking: Field 2
Blanking: Field 1
625 Line / 50 Hz
Figure
Philips Semiconductors
7-22.
1
.