MC9328MX21VG Freescale, MC9328MX21VG Datasheet - Page 20

• Manufacturer Part Number: MC9328MX21VG
• Manufacturer: Freescale

Specifications of MC9328MX21VG

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Specifications
The output External Grant signal from the DMAC is an active-low signal.When the following conditions
are true, the External DMA Grant signal is asserted with the initiation of the DMA burst.
After the grant is asserted, the External DMA request will not be sampled until completion of the DMA
burst. As the external request is synchronized, the request synchronization will not be done during this
period. The priority of the external request becomes low for the next consecutive burst, if another DMA
request signal is asserted.
Worst case—that is, the smallest burst (1 byte read/write) timing diagrams are shown in
Figure
in
Figure 4
DMA request is de-asserted immediately after sensing grant signal active.
Figure 5
sensing grant signal active such that a new burst is not initiated.
20
Table
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5. Minimum and maximum timings for the External request and External grant signals are present
The DMA channel for which the DMA burst is ongoing has request source as external DMA
Request
(as per source select register setting).
REN and CEN bit of this channel are set.
External DMA Request is asserted.
13.
shows the minimum time for which the External Grant signal remains asserted when an External
shows the safe maximum time for which External DMA request can be kept asserted, after
External device
External device
Ext_DMAGrant
Data read from
Data written to
Ext_DMAReq
Ext_DMAGrant
Ext_DMAReq
NOTE: Assuming in worst case the data is read/written from/to External device as per the above waveform.
Figure 5. Safe Maximum Timings for External Request De-Assertion
Figure 4. Assertion of DMA External Grant Signal
MC9328MX21 Technical Data, Rev. 3.4
t
max_req_assert
t
min_assert
t
max_read
Freescale Semiconductor
t
max_write
Figure 4
and