MC9328MX21SCVM Freescale, MC9328MX21SCVM Datasheet - Page 2

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MC9328MX21SCVM

Manufacturer Part Number
MC9328MX21SCVM
Description
Manufacturer
Freescale
Datasheet

Specifications of MC9328MX21SCVM

Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant

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Introduction
devices to be used as primary or secondary non-volatile storage. The on-chip error correction code (ECC)
and parity checking circuitry of the NAND Flash controller frees the CPU for other tasks. WLAN,
Bluetooth and expansion options are provided through PCMCIA/CF, USB, and MMC/SD host controllers.
The device is packaged in a 289-pin MAPBGA.
1.1
This document uses the following conventions:
2
Standard System I/O
Clock Management
System Control
OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.
Logic level one is a voltage that corresponds to Boolean true (1) state.
Logic level zero is a voltage that corresponds to Boolean false (0) state.
To set a bit or bits means to establish logic level one.
To clear a bit or bits means to establish logic level zero.
A signal is an electronic construct whose state conveys or changes in state convey information.
A pin is an external physical connection. The same pin can be used to connect a number of signals.
Asserted means that a discrete signal is in active logic state.
— Active low signals change from logic level one to logic level zero.
— Active high signals change from logic level zero to logic level one.
Negated means that an asserted discrete signal changes logic state.
— Active low signals change from logic level zero to logic level one.
— Active high signals change from logic level one to logic level zero.
JTAG/Multi- ICE
System Boot
Conventions
Timers x 3
WDOG
DMAC
PWM
GPIO
RTC
®
Figure 1. i.MX21S Functional Block Diagram
Human Interface
SLCD Controller
Internal Control
LCD Controller
MC9328MX21S Technical Data, Rev. 1.3
ARM926EJ-S
D Cache
I Cache
Keypad
ARM9 Platform
i.MX21S
Memory Control
Memory Interface
Bus Control
MMU
SDRAMC
MAX
WEIM
NFC
Memory Expansion
USB OTG/ 1 Host
Connectivity
UART 1, 3, & 4
Audio Mux
MMC/SD x 2
PCMCIA/CF
CSPI x 2
Freescale Semiconductor
1-Wire
SSI x 2
FIRI
I
2
C

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