ATR0621P-7FHW Atmel, ATR0621P-7FHW Datasheet
ATR0621P-7FHW
Specifications of ATR0621P-7FHW
Related parts for ATR0621P-7FHW
ATR0621P-7FHW Summary of contents
Page 1
... Core Supply Voltage • Includes Power Supervisor • 1.8V to 3.3V User-definable I/O Voltage for Several GPIOs with 5V Tolerance • 4 Kbytes Battery Backup Memory • 100-pin BGA Package (LFBGA100) • RoHS-compliant ® Processor Core GPS Baseband Processor ATR0621P 4890H–GPS–08/08 ...
Page 2
... A-GPS (aiding also possible to store the configuration settings in an optional external EEPROM. The ATR0621P is manufactured using the Atmel the ARM7TDMI microcontroller core with on-chip SRAM, 16-channel GPS correlator and a wide range of peripheral functions on a monolithic chip, the ATR0621P provides a highly-flexible and cost-effective solution for GPS applications. ATR0621P 2 ® ...
Page 3
... P2/BOOT_MODE P30/AGCOUT0 P8/STATUSLED P16/NEEPROM P11/EM_A21 P28/EM_A20 P10/EM_A0/NLB P7/NUB/NWR1 P6/NOE/NRD P5/NWE/NWR0 P4/nCS0 P3/nCS1 EM_A19 EM_A1 EM_DA15 EM_DA0 DBG_EN NTRST TDI TDO TCK TMS NRESET 4890H–GPS–08/08 ATR0621P SIGLO0 SIGHI0 P21/TXD2 P22/RXD2 P18/TXD1 P31/RXD1 USB_DP USB_DM VBAT18 VBAT LDOBAT_IN LDO_OUT LDO_IN LDO_EN 3 ...
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... As a result, the performance of the microcontroller is increased and the power consumption reduced. The ATR0621P peripherals are designed to be easily programmable with a minimum number of instructions. Each peripheral has a 16 Kbyte address space allocated in the upper 3 Mbyte of the 4 Gbyte address space. (Except for the interrupt controller, which has 4 Kbyte address space ...
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... Pin Configuration 3.1 Pinout Figure 3-1. Pinout LFBGA100 (Top View) Table 3-1. ATR0621P Pinout Pin Name LFBGA100 Pin Type CLK23 G9 IN DBG_EN H4 IN EM_A1 A6 OUT EM_A2 A5 OUT EM_A3 A4 OUT EM_A4 A2 OUT EM_A5 A3 OUT EM_A6 B5 OUT EM_A7 B4 OUT EM_A8 B2 OUT EM_A9 D4 OUT ...
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... Table 3-1. ATR0621P Pinout (Continued) Pin Name LFBGA100 Pin Type EM_A16 C6 OUT EM_A17 F8 OUT EM_A18 B3 OUT EM_A19 C5 OUT EM_DA0 B6 I/O EM_DA1 B10 I/O EM_DA2 C7 I/O EM_DA3 C10 I/O EM_DA4 D10 I/O EM_DA5 E7 I/O EM_DA6 E9 I/O EM_DA7 B7 I/O EM_DA8 B8 I/O EM_DA9 A9 I/O ...
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... Table 3-1. ATR0621P Pinout (Continued) Pin Name LFBGA100 Pin Type I/O P10 E4 I/O P11 H10 I/O P12 F3 I/O P13 G10 I/O P14 J5 I/O P15 K5 I/O P16 E1 I/O P17 J4 I/O P18 K4 I/O P19 F1 I/O P20 H2 I/O P21 F2 I/O ...
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... Table 3-1. ATR0621P Pinout (Continued) Pin Name LFBGA100 Pin Type TDI J2 IN TDO K3 OUT TMS J1 IN USB_DM F10 I/O USB_DP D3 I/O VBAT J7 IN (2) VBAT18 G6 OUT VDD18 E6 IN VDD18 F7 IN VDD18 F6 IN (3) VDDIO E5 IN (4) VDD_USB F5 IN XT_IN J9 IN XT_OUT J10 OUT (5) NC ...
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... Signal Description Table 3-2. ATR0621P Signal Description Module Name Function EM_A0 to EM_A21 External memory address bus EM_DA0 to EM_DA15 External memory data bus NCS0 to NCS1 Chip select NCS2 to NCS3 Chip select NWR0 Lower byte write signal NWR1 Upper byte write signal ...
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... Table 3-2. ATR0621P Signal Description (Continued) Module Name Function SIGHI0 Digital IF SIGLO0 Digital IF GPS SIGHI1 Digital IF SIGLO1 Digital IF TIMEPULSE GPS synchronized time pulse GPSMODE0-12 GPS mode STATUSLED Status LED NEEPROM Enable EEPROM support CONFIG ANTON Active antenna power on output Active antenna short circuit ...
Page 11
... GPSMODE pins after system reset. Alternatively, the system can be configured through message commands passed through the serial interface after start-up. This configuration of the ATR0621P can be stored in an external non-volatile memory like FLASH memory or EEPROM. Default designates settings used by ROM firmware if GPSMODE configu- ration is disabled (GPSMODE0 =0) ...
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... Serial I/O Configuration The ATR0621P features a two-stage I/O message and protocol selection procedure for the two available serial ports. At the first stage, a certain protocol can be enabled or disabled for a given USART port or the USB port. Selectable protocols are RTCM, NMEA and UBX. At the second stage, messages can be enabled or disabled for each enabled protocol on each port ...
Page 13
... Part of Output Data) Standard GGA, RMC, GSA, GSV, GLL, VTG, ZDA, GRS, GST Proprietary PUBX00, PUBX03, PUBX04 SOL, SVINFO, POSECEF, POSLLH, STATUS, DOP, VELECEF, NAV VELNED, TIMEGPS, TIMEUTC, CLOCK MON SCHD, IO, IPC, EXCEPT RXM RAW (RAW message support requires an additional license) ATR0621P 13 ...
Page 14
... P15/ANTON assumed that also input P25/NAADET0/MISO will signal zero DC current, i.e. switch to its active low state. Which pin is used as NAADET (P14 or P25) depends on the settings of GPSMODE11 and GPSMODE10 (see page ATR0621P 14 Serial I/O Default Setting if GPSMODE Configuration is Deselected (GPSMODE0 = 0) ...
Page 15
... Low = Power supply to active antenna is switched off Comment P25/NAADET0/MISO P25/NAADET0/MISO Reserved for further use. P14/NAADET1 Do not use this setting. P14/NAADET1 (Default ROM value) Reserved for further use. P14/NAADET1 Do not use this setting. Reserved for further use. P14/NAADET1 Do not use this setting. P25/NAADET0/MISO P25/NAADET0/MISO ATR0621P 15 ...
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... TMS NC TCK NC TDI NC NTRST NC TDO NC DBG_EN GND GND NSHDN LDO_EN LDO_OUT VDD18 LDO_IN LDOBAT_IN VBAT18 VBAT +3V ATR0621P P8 STATUS LED P20 TIMEPULSE USB_DM Optional USB_DP USB P31 Optional USART 1 P18 P22 Optional USART 2 P21 XT_IN 32.368 kHz (see RTC) XT_OUT +3V (see Power Supply) ...
Page 17
... P23/GPSMODE7/SCK user application. Refer to GPSMODE definitions in section page 11. 4890H–GPS–08/08 “Setting GPSMODE0 to GPSMODE12” on page ATR0621P 11. Can be left open if configured as output by “Setting GPSMODE0 to GPSMODE12” on “Setting GPSMODE0 to GPSMODE12” on “Setting GPSMODE0 to GPSMODE12” on “Setting GPSMODE0 to GPSMODE12” on “Setting GPSMODE0 to GPSMODE12” on ...
Page 18
... Internal pull-down resistor, leave open. P31/RXD1 Internal pull-up resistor, leave open if serial interface is not used. EM_DA0 – EM_DA15 If no external memory is used, could be leave open (internal pull-down). ATR0621P 18 “Setting GPSMODE0 to GPSMODE12” on “Setting GPSMODE0 to GPSMODE12” on “Setting GPSMODE0 to GPSMODE12” on “Setting GPSMODE0 to GPSMODE12” on ...
Page 19
... FLASH memory. The 32-bit RISC processor of the ATR0621 accesses the external memory via the EBI (External Bus Interface). Atmel recommends to use 1.8V FLASH memory, e.g. the Atmel AT49SV802A. The LDO_OUT pin of the ATR0621P can supply the external FLASH memory. ...
Page 20
... Connecting an Optional Serial EEPROM The ATR0621P offers the possibility to connect an external serial EEPROM. The internal ROM firmware supports to store the configuration of the ATR0621P in serial EEPROM. The pin P16/NEEPROM signals the firmware that a serial EEPROM is connected with the ATR0621P. The 32-bit RISC processor of the ATR0621P accesses the external memory with SPI (Serial Peripheral Interface) ...
Page 21
... Figure 4-3 show examples of the wiring of ATR0621 power supply. External Wiring Example Using Internal LDOs and Backup Power Supply NSHDN 1 µF (X7R) 1.5V to 3.6V 1 µF (X7R 3.6V ATR0621P ATR0621P internal LDO18 ldoin LDO_IN ldoen LDO_EN ldoout LDO_OUT Core VDD18 1.8V to 3.3V ...
Page 22
... Figure 4-2. 1.65V to 1.95V 2.3V to 3.6V ATR0621P 22 External Wiring Example Using 1.8V from Host System and Backup Power Supply 1 µF (X7R) 1.5V to 3.6V 1 µF (X7R 3.6V ATR0621P internal LDO18 ldoin LDO_IN ldoen LDO_EN ldoout LDO_OUT Core VDD18 1.8V to 3.3V VDDIO variable IO Domain ...
Page 23
... LDO_IN NSHDN LDO_EN LDO_OUT VDD18 1 µF (X7R) VDDIO LDOBAT_IN 1.5V to 3.6V VBAT VBAT18 1 µF (X7R) VDDUSB ATR0621P ATR0621P internal LDO18 ldoin ldoen ldoout Core 1.8V to 3.3V variable IO Domain LDOBAT ldobat_in vbat vbat18 vdd RTC Backup Memory USB SM and Transceiver ...
Page 24
... P3 to P7, P10, P11, P15, P28, P30, SIGHI, SIGLO, CLK23, XT_IN, TMS, TCK, TDI, NTRST, DBG_EN, LDO_EN, NRESET USB_DM, USB_DP P1, P2, P8, P9, P12 to P14, P16 to P27, P29, P31 Symbol R thJA ATR0621P internal RTC Min. Max. Unit –40 +85 °C –60 +150 °C –0.3 +1 ...
Page 25
... VDD18 0.3 V th-,CLK23 VDD18 V 0.2 0.55 hyst,CLK23 V 0.8 1.3 th+,NRESET V 0.46 0.77 th-,NRESET V –0.3 +0.41 IL,IO V 1.46 5.0 IH,IO V –0.3 +0.41 IL,BAT V 1.46 5.0 IH,BAT V –0.3 +0.8 IL,USB V 2.0 4.6 IH,USB V 0.4 OL,18 VDD18 V OH,18 – 0.45 ATR0621P Unit Type ...
Page 26
... VDDIO is the supply voltage for the following GPIO-pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29 2. Values defined for operating the USB interface. Otherwise VDD_USB may be connected to ground 3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT ATR0621P 26 Pin = 1.5 mA, = – ...
Page 27
... Table 9-1. Mode Sleep Shutdown Normal *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter 10. ESD Sensitivity The ATR0621P is an ESD sensitive device. Observe precautions for handling. Table 10-1. Test Model Human Body Model (HBM) 4890H–GPS–08/08 Pin Symbol ...
Page 28
... Output current (VBAT18) No external load allowed Current consumption LDOBAT_IN Current consumption (1) VBAT Current consumption *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter Note: ATR0621P 28 Electrical Characteristics of LDO18 Conditions After startup, no load, at room temperature Standby mode (LDO_EN = 0), at room temperature Electrical Characteristics of LDOBAT Conditions ...
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... Ordering Information Extended Type Number Package ATR0621P-7FQY LFBGA100 ATR0621P-7FHW LFBGA100 ATR0622-EK1 ATR0622-DK1 14. Package LFBGA100 Package: R-LFBGA 100_G Dimensions Corner Top View technical drawings according to DIN specifications Drawing-No.: 6.580-5003.01-4 Issue: 2; 27.10.05 Moisture sensitivity level (MSL 4890H–GPS–08/08 MPQ Remarks 2000 9 mm ...
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... Table 3-1 “ATR0621P Pinout” on page 5 changed Section 13 “Ordering Information” on page 29 changed Table 3-1 “ATR0621P Pinout” on page 5 changed Section 8 “Electrical Characteristics” numbers 1.35 and 1.36 on page 26 changed All pages: Part number changed in ATR0621P Page 24: Abs ...
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