TS68882MF1-20 E2V, TS68882MF1-20 Datasheet - Page 23

• Manufacturer Part Number: TS68882MF1-20
• Manufacturer: E2V

Specifications of TS68882MF1-20

• Operating Temperature (max): 125C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

8.3
e2v semiconductors SAS 2007
Co-processor Interface
When used as a peripheral processor with the 8-bit TS68008 or the 16-bit TS68000, or TS68010, all
TS68882 instructions are trapped by the main processor to an exception handler at execution time.
Thus, the software emulation of the processor interface protocol can be totally transparent to the user.
The system can be quickly upgraded by replacing the main processor with a TS68020/TS68030 without
changes to the user software.
Since the bus is asynchronous, the TS68882 need not run at the same clock speed as the main proces-
sor. Total system performance may therefore be customized. For example, a system requiring very fast
floating-point arithmetic with relatively slow integer arithmetic can be designed with an inexpensive main
processor and a fast TS68882.
The TS68000 Family co-processor interface is an integral part of the TS68882 and TS68020/TS68030
designs, with the interface tasks shared between the two. The interface is fully compatible with all
present and future TS68000 Family products. Tasks are partitioned such that the TS68020/TS68030
does not have to decode co-processor instructions and, the TS68882 does not have to duplicate main
processor functions such as effective address evaluation.
This partitioning provides an orthogonal extension of the instruction set by permitting TS68882 instruc-
tions to utilize all TS68020/TS68030 addressing modes and to generate execution time exception traps.
Thus, from the programmer’s view, the CPU and co-processor appear to be integrated onto a single
chip. While the execution of the majority of TS68882 instructions may be overlapped with the execution
of TS68020/TS68030 instructions, concurrency is completely transparent to the programmer. The
TS68020/TS68030 single-step and program flow (trace) modes are fully supported by the TS68882 and
the TS68000 Family co-processorco-processor interface.
While the TS68000 Family co-processor interface permits co-processors to be bus masters, the
TS68882 is never a bus master. The TS68882 requests that the TS68020/TS68030 fetch all operands
and store all results. In this manner, the TS68020/TS68030 32-bit data bus provides high speed transfer
of floating-point operands and results while simplifying the design of the TS68882.
Since the co-processor interface is based solely upon bus cycles and the TS68882 is never a bus mas-
ter, the TS68882 can be placed on either the logical or physical side of the system memory management
unit. This provides a great deal of flexibility in the system design.
The virtual machine architecture of the TS68000 Family is supported by the co-processor interface and
the TS68882 through the FSAVE and FRESTORE instructions. If the TS68020/TS68030 detects a page
fault and/or task time out, it can force the TS68882 to stop whatever operation is in process at any time
(even in the middle of the execution of an instruction) and save the TS68882 internal state in memory.
The size of the saved internal state of the TS68882 is dependent upon what the CCU and ECU are doing
at the time that the FSAVE is executed. If the TS68882 is in the reset state when the FSAVE instruction
is received, only one word of state is transferred to memory, which may be examined by the operating
system to determine that the co-processor programmer’s model is empty. If the co-processor is idle
when the save instruction is received, only a few words of internal state are transferred to memory. If the
TS68882 is in the middle of performing a calculation, it may be necessary to save the entire internal state
of the machine. Instructions that can complete execution in less time than it would take to save the larger
state in mid-instruction are allowed to complete execution and then save the idle state.
Thus the size of the saved internal state is kept to a minimum. The ability to utilize several internal state
sizes greatly reduces the average context switching time.
0852B–HIREL–06/07
TS68882
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