TS68882MR33 E2V, TS68882MR33 Datasheet - Page 32

• Manufacturer Part Number: TS68882MR33
• Manufacturer: E2V

Specifications of TS68882MR33

• Operating Temperature (max): 125C
• Operating Temperature Classification: Military
• Lead Free Status / RoHS Status: Compliant

8.18
8.19
8.20
8.21
8.22
32
Data Bus (D0 through D31)
Size (SIZE)
Address Strobe (AS)
Chip Select (CS)
Read/Write (R/W)
0852B–HIREL–06/07
Table 8-3.
Table 8-4.
This 32-bit, bi-directional, three-state bus serves as the general-purpose data path between the
TS68020/TS68030 and the TS68882. Regardless of whether the TS68882 is operated as a co-proces-
sor or a peripheral processor, all inter-processor transfers of instruction information, operand data,
status information, and requests for service occur as standard TS68000 bus cycles.
The TS68882 will operate over an 8-, 16-, or 32-bit system data bus. Depending upon the system data
bus configuration, both the A0 and SIZE pins are configured specifically for the applicable bus configura-
tion. (Refer to ADDRESS BUS (A0 through A4) and SIZE (SIZE for further details).
This active-low input signal is used in conjunction with the A0 pin to configure the TS68882 for operation
over an 8-, 16-, or 32-bit system data bus. When the TS68882 is configured to operate over a 16-or 32-
bit system data bus, both the SIZE and A0 pins are strapped high and/or low as listed in
This active-low input signal indicates that there is a valid address on the address bus, and both the chip
select (CS) and read/write (R/W signal lines are valid).
This active-low input signal enables the main processor access to the TS68882 co-processor interface
registers. When operating the TS68882 as a peripheral processor, the chip select decode is system
dependent (i.e., like the chip select on any peripheral). The CS signal must be valid (either asserted or
negated) when AS is asserted. Refer to CHIP SELECT TIMING for further discussion of timing restric-
tions for this signal.
This input signal indicates the direction of a bus transaction (read/write) by the main processor. A logic
high (1) indicates a read from the TS68882, and a logic low (0) indicates a write to the TS68882. The
R/W signal must be valid when AS is asserted.
A4-A0
1011x
110xx
111xx
Co-processor Interface Register Selection
System Data Bus Size Configuration
High
Low
A0
Offset
S1C
S16
S18
Width
High
High
Size
Low
16
32
32
Type
Read
R/W
-
e2v semiconductors SAS 2007
Data bus
16-bit
32-bit
8-bit
Register
(Reserved)
Instruction Address
Operand Address
Table
TS68882
8-4.