TS68882MF25 E2V, TS68882MF25 Datasheet - Page 13

• Manufacturer Part Number: TS68882MF25
• Manufacturer: E2V

Specifications of TS68882MF25

• Operating Temperature (max): 125C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Table 7-3.
Notes:
e2v semiconductors SAS 2007
N°
21
22
23
24
25
26
27
1. Timing measurements are referenced to and from a low voltage of 0.8V and a high voltage of 2.0V, unless otherwise noted.
2. These specifications only apply if the TS68882 has completed all internal operations initiated by the termination of the previ-
3. Synchronous read cycles occur only when the save or response CIR locations are read.
4. This specification only applies to systems in which back-to-back accesses (read-write or write-write) of the operand CIR can
5. If the SIZE pin is not strapped to either V
6. If the SIZE pin is not strapped to either V
7. This number is reduced to 5 nanoseconds if DSACK0 and DSACK1 have equal loads.
8. START is not an external signal; rather, it is the logical condition that indicates the start of an access. The logical equation for
9. If a subsequent access is not a FPCP access, CS must be negated before the assertion of AS and/or DS on the non-FPCP
Parameter
START false to DSACK0 and DSACK1
negated
START false to DSACK0 and DSACK1
high impedance
START true to clock high (synchronous
read)
Clock low to data-out valid synchronous
read)
START true to data-out valid (synchronous
read)
Clock low to DSACK0 and DSACK1
asserted (synchronous read
START true to DSACK0 and DSACK1
asserted (synchronous read)
The voltage swing through this range should start outside, and pass through, the range such that the rise or fall will be linear
between 0.8V and 2.0V.
ous bus cycle when DS was negated.
occur. When the TS68882 is used as a co-processor to the TS68020/68030, this can occur when the addressing mode is
immediate.
this condition is START = CS + AS + (R/W · DS).
access. These specifications replace the old specifications 8 and 8A (the old specifications implied that in all cases, transi-
tions in CS must not occur simultaneously with transitions of AS or DS. This is not a requirement of the TS68882).
(3)(8)
(3)
(3)(8)
AC Electrical Characteristics – Read and Write Cycles
V
Figure 7-5 on page
CC
(8)
= 5.0 V
(8)
DC
± 10%; GND = 0 V
17,
(3)
(3)(8)
Figure 7-6 on page
DC;
CC
CC
or GND, it must have the same setup times as do addresses.
or GND, it must have the same hold times as do addresses.
Tc = -55°C/+125°C or Tc = -40°C/+85°C (see
Min
1.5
1.5
16.67 MHz
0
0
18)
105+
Max
105
75+
2.5
2.5
50
70
75
Min
1.5
1.5
(1)
0
20 MHz
(Continued)
80 +
Max
55+
2.5
2.5
30
55
80
55
Min
1.5
1.5
0
25 MHz
Max
60+
45+
2.5
2.5
40
55
60
45
Figure 7-4 on page
0852B–HIREL–06/07
Min
1.5
1.5
33.33 MHz
0
TS68882
Max
45-
30-
2.5
2.5
30
40
45
30
Unit
Clks
Clks
16,
ns
ns
ns
ns
ns
ns
ns
13