TS68882MR1-20 E2V, TS68882MR1-20 Datasheet - Page 19

• Manufacturer Part Number: TS68882MR1-20
• Manufacturer: E2V

Specifications of TS68882MR1-20

• Operating Temperature (max): 125C
• Operating Temperature Classification: Military
• Lead Free Status / RoHS Status: Not Compliant

8. Functional Description
8.1
e2v semiconductors SAS 2007
The Co-processor Concept
The TS68882 functions as a co-processor in systems where the TS68020 or TS68030 is the main pro-
cessor via the TS68000 co-processor interface. It functions as a peripheral processor in systems where
the main processor is the TS68000, TS68010.
The TS68882 utilizes the TS68000 Family co-processor interface to provide extension of the TS68020
/TS68030 registers and instruction set in a manner which is transparent to the programmer. The pro-
grammer perceives the MPU/FPCP execution model as if both devices are implemented on one chip.
A fundamental goal of the TS68000 Family co-processor interface is to provide the programmer with an
execution model based upon sequential instruction execution by the TS68020/TS68030 and the
TS68882. For optimum performance, however, the co-processor interface allows concurrent operations
in the TS68882 with respect to the TS68020/TS68030 whenever possible. In order to simplify the pro-
grammer’s model, the co-processor interface is designed to emulate, as closely as possible, non-
concurrent operation between the TS68020/TS68030 and the TS68882.
The TS68882 is s non-DMA type co-processor which uses a subset of the general-purpose co-processor
interface supported by the TS68020/TS68030. Features of the interface implemented in the TS68882
are as follows:
The TS68882 programming model is shown in
following:
• The main processor(s) and TS68882 communicate via standard TS68000 bus cycles
• The main processor(s) and TS68882 communications are not dependent upon the instruction sets or
• The main processor(s) and TS68882 may operate at different clock speeds
• TS68882 instructions utilize all addressing modes provided by the main processor; all effective
• All data transfers are performed by the main processor at the request of the TS68882; thus memory
• Overlapped (concurrent) instruction execution enhances throughput while maintaining the
• Co-processor detection of exceptions which require a trap to be taken are serviced by the main
• Support of virtual memory/virtual machine systems is provided via the FSAVE and FRESTORE
• Up to eight co-processors may reside in a system simultaneously: multiple co-processors of the same
• Systems may use software emulation of the TS68882 without reassembling or relinking user software
• Eight 80-bit floating-point data registers (FP0-FP7). These registers are analogous to the integer data
• A 32-bit control register that contains enable bits for each class of exceptions trap, and mode bits to
internal details of the individual devices (i.e., instruction pipes or caches, addressing modes)
addresses are calculated by the main processor at the request of the co-processor
management, bus errors, address errors, and bus arbitration function as if the TS68882 instructions
are executed by the main processor
programmer’s model of sequential instruction execution
processor at the request of the TS68882 thus exception processing functions as if the TS68882
instructions were executed by the main processor
instructions
type are also allowed
registers (D0-D7) and are completely general-purpose (i.e., any instruction may use any register)
set the user-selectable rounding and precision modes
Figure 8-1 on page 20
through 15, and consists of the
0852B–HIREL–06/07
TS68882
19